| Line 113... |
Line 113... |
`shift : EBX<={EBX[31:5],EBX_shtr};
|
`shift : EBX<={EBX[31:5],EBX_shtr};
|
`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
|
`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
|
`div1 : EBX<={ 2'b00,EBX[29:0]};
|
`div1 : EBX<={ 2'b00,EBX[29:0]};
|
`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
|
`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
|
`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
|
`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
|
default : if (ID[15:8] == 8'hb3) EBX<= {EBX[31:24],ID[7:0]};
|
`fetch : if (ID[15:8] == 8'hb3) EBX<= {EBX[31:24],ID[7:0]};
|
else if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
|
else if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
|
|
default : EBX <= EBX;
|
endcase
|
endcase
|
case(state) // ECX control
|
case(state) // ECX control
|
`init : ECX <= 32'b0;
|
`init : ECX <= 32'b0;
|
`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
|
`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
|
`sml1,`sdv1 : ECX <= smlECX;
|
`sml1,`sdv1 : ECX <= smlECX;
|
| Line 135... |
Line 136... |
`sdv3 : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
|
`sdv3 : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
|
`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
|
`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
|
default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
|
default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
|
endcase
|
endcase
|
case(state) // ESP control
|
case(state) // ESP control
|
`init : ESP <= 32'h0161fc;
|
`init : ESP <= 32'h0191fc;
|
`call,`calla,`int1 : ESP <= ESP - 4'b0100;
|
`call,`calla,`int1 : ESP <= ESP - 4'b0100;
|
`ret2 : ESP <= ESP + 4'b0100;
|
`ret2 : ESP <= ESP + 4'b0100;
|
default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
|
default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
|
endcase
|
endcase
|
if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
|
if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
|
| Line 313... |
Line 314... |
(state == `calla2)? 1'b0 : 1'b1 ;
|
(state == `calla2)? 1'b0 : 1'b1 ;
|
assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
|
assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
|
{ {24{regsrc[7] }} , regsrc[7:0] } ;
|
{ {24{regsrc[7] }} , regsrc[7:0] } ;
|
assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
|
assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
|
{ 24'b0 , regsrc[7:0] } ;
|
{ 24'b0 , regsrc[7:0] } ;
|
assign BEN =((state == `call2)|(state == `calla2)) ? 1'b1 : { prefx , ID[8] } ;
|
assign BEN = (state == `fetch) ? { prefx , ID[8] } : 1'b1;
|
|
//assign BEN =((state == `call2)|(state == `calla2)) ? 1'b1 : { prefx , ID[8] } ;
|
assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
|
assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
|
assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
|
assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
|
assign naF = ~(nlF | neqF );
|
assign naF = ~(nlF | neqF );
|
assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
|
assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
|
assign ngF = ~(nbF | neqF );
|
assign ngF = ~(nbF | neqF );
|
