| Line 42... |
Line 42... |
`define jne2 5'b11000
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`define jne2 5'b11000
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`define mul 5'b11001
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`define mul 5'b11001
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`define mul2 5'b11010
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`define mul2 5'b11010
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always @(posedge CLK or negedge RSTN)
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always @(posedge CLK or negedge RSTN)
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if(!RSTN) begin
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if(!RSTN) begin
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EAX <= 32'b0; EBX <= 32'b0; ECX <= 32'b0; EDX <= 32'b0;
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ESP <= 32'b011111111; PC <= 32'b0;
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EBP <= 32'b0; ESP <= 32'b011111111; PC <= 32'b00000;
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eqF <= 1'b0; lF <= 1'b0; gF <= 1'b0;
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eqF <= 1'b0; lF <= 1'b0; gF <= 1'b0;
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state <=5'b00000; prefx <= 1'b0; cry <= 1'b0;
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state <=5'b0; prefx <= 1'b0; cry <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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state <= nstate; prefx <= nprefx; cry <= ncry;
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state <= nstate; prefx <= nprefx; cry <= ncry;
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case (cmpr)
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case (cmpr)
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| Line 66... |
Line 65... |
if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;
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end
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end
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else if (state==`mul)
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else if (state==`mul)
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begin
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begin
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EAX <= {EAX[30:0],1'b0};
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EAX <= {EAX[30:0],1'b0};
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if (EDX[0] == 1'b1) EBX <= EBX + EAX; else EBX <= EBX;
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if (EDX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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EDX <= {1'b0,EDX[31:1]};
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EDX <= {1'b0,EDX[31:1]};
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ECX <= ECX; ESP <= ESP; EBP <= EBP;
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ECX <= ECX; ESP <= ESP; EBP <= EBP;
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end
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end
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else if (state==`mul2)
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else if (state==`mul2)
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begin
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begin
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| Line 129... |
Line 128... |
3'b101 : regdest = EBP;
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3'b101 : regdest = EBP;
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3'b111 : regdest = D ;
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3'b111 : regdest = D ;
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default: regdest = EBX;
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default: regdest = EBX;
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endcase
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endcase
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// alu
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// alu
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always@(regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
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always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
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begin
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if (state == `fetch )
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case (ID[15:10])
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case (ID[15:10])
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6'b000000 : {ncry,alu_out} = adder_out ; // ADD , carry generation
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6'b000000 : {ncry,alu_out} = adder_out ; // ADD , carry generation
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6'b000010 : {ncry,alu_out} = {cry,regdest | regsrc}; // OR
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6'b000010 : {ncry,alu_out} = {cry,regdest | regsrc}; // OR
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6'b000100 : {ncry,alu_out} = adder_out ; // ADD , carry use
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6'b000100 : {ncry,alu_out} = adder_out ; // ADD , carry use
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6'b000110 : {ncry,alu_out} = sub_out ; // SUB , carry use
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6'b000110 : {ncry,alu_out} = sub_out ; // SUB , carry use
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| Line 146... |
Line 145... |
6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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endcase
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endcase
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end
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else {ncry,alu_out} = {cry,regdest };
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// Main instruction decode
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// Main instruction decode
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always @(ID,state,EDX)
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always @(ID,state,EDX)
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begin
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begin
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// One cycle instructions, operand selection
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// One cycle instructions, operand selection
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if (state == `fetch)
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if (state == `fetch)
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| Line 216... |
Line 215... |
assign A = (state == `call2) ? ESP : EBX ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign shtr = ID[12] ? ECX[4:0] : EBX[4:0] ;
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assign shtr = ID[12] ? ECX[4:0] : EBX[4:0] ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign WEN = (ID[15:8]==8'h90) ? 1'b1 :
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assign WEN = (ID[15:8]==8'h90) ? 1'b1 :
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(state == `call2) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(dest == 3'b111) ? 1'b0 :
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(dest == 3'b111) ? 1'b0 : 1'b1 ;
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1'b1 ;
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assign tst = sft_in >>> (shtr);
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assign tst = sft_in >>> (shtr);
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assign sft_out = (src == 3'b111) ? tst : //sar
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assign sft_out = (src == 3'b111) ? tst : //sar
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(src == 3'b101) ? (sft_in >> shtr ) : //shr
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(src == 3'b101) ? (sft_in >> shtr ) : //shr
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(sft_in << shtr ) ; //shl
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(sft_in << shtr ) ; //shl
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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| Line 241... |
Line 239... |
assign pc_eq = ( eqF ) ? pc_jp : incPC;
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assign pc_eq = ( eqF ) ? pc_jp : incPC;
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assign pc_neq = ( eqF ) ? incPC : pc_jp;
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assign pc_neq = ( eqF ) ? incPC : pc_jp;
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assign pc_jp = incPC+{ID,EBX[15:0]};
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assign pc_jp = incPC+{ID,EBX[15:0]};
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assign adder_out= nncry + regsrc + regdest;
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assign adder_out= nncry + regsrc + regdest;
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assign sub_out= regdest - regsrc - nncry;
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assign sub_out= regdest - regsrc - nncry;
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assign nncry = ID[12] ? cry : 1'b0;
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assign nncry = (ID[12] ? cry : 1'b0);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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