| Line 5... |
Line 5... |
output [31:0] A;
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output [31:0] A;
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input [31:0] D;
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input [31:0] D;
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output [31:0] Q;
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output [31:0] Q;
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output WEN;
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output WEN;
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output [1:0] BEN;
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output [1:0] BEN;
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wire nncry,neqF,ngF,nlF;
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wire nncry,neqF,ngF,nlF,naF,nbF;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [4:0] state,nstate;
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reg [5:0] state,nstate;
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wire [4:0] shtr;
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reg [2:0] src,dest;
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reg [2:0] src,dest;
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reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF;
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reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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wire [31:0] incPC,Sregsrc,Zregsrc,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
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wire signed [31:0] sft_in,sft_out,tst;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [32:0] adder_out,sub_out;
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wire [32:0] adder_out,sub_out;
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`define fetch 5'b00000
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wire [4:0] EBX_shtr;
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`define jmp 5'b00001
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wire signed [31:0] ssregsrc, ssregdest;
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`define jmp2 5'b00010
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`define fetch 6'b111111
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`define jge 5'b00011
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`define jmp 6'b000001
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`define jge2 5'b00100
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`define jmp2 6'b000010
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`define imm 5'b00101
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`define jge 6'b000011
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`define imm2 5'b00110
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`define jge2 6'b000100
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`define lea 5'b00111
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`define imm 6'b000101
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`define lea2 5'b01000
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`define imm2 6'b000110
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`define call 5'b01001
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`define lea 6'b000111
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`define call2 5'b01010
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`define lea2 6'b001000
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`define ret 5'b01011
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`define call 6'b001001
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`define ret2 5'b01100
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`define call2 6'b001010
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`define shift 5'b01110
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`define ret 6'b001011
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`define jg 5'b01111
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`define ret2 6'b001100
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`define jg2 5'b10000
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`define shift 6'b001110
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`define jl 5'b10001
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`define jg 6'b001111
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`define jl2 5'b10010
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`define jg2 6'b010000
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`define jle 5'b10011
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`define jl 6'b010001
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`define jle2 5'b10100
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`define jl2 6'b010010
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`define je 5'b10101
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`define jle 6'b010011
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`define je2 5'b10110
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`define jle2 6'b010100
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`define jne 5'b10111
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`define je 6'b010101
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`define jne2 5'b11000
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`define je2 6'b010110
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`define mul 5'b11001
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`define jne 6'b010111
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`define mul2 5'b11010
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`define jne2 6'b011000
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always @(posedge CLK or negedge RSTN)
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`define mul 6'b011001
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if(!RSTN) begin
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`define mul2 6'b011010
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ESP <= 32'b011111111; PC <= 32'b0;
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`define shft2 6'b011011
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eqF <= 1'b0 ; lF <= 1'b0 ; gF <= 1'b0;
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`define jb 6'b011100
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state <=5'b0; prefx <= 1'b0; cry <= 1'b0;
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`define jb2 6'b011101
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end
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`define jbe 6'b011110
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else
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`define jbe2 6'b011111
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`define ja 6'b100000
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`define ja2 6'b100001
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`define jae 6'b100010
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`define jae2 6'b100011
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`define sml1 6'b100100
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`define sml2 6'b100101
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`define sml3 6'b100110
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`define sml4 6'b100111
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`define init 6'b000000
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always @(posedge CLK)
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begin
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begin
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state <= nstate; prefx <= nprefx; cry <= ncry;
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case (state) // cry control
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case (cmpr)
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`sml1 : cry <= EAX[31] ^ ECX[31];
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1'b1 : begin eqF <= neqF ; lF <= nlF; gF <= ngF; end
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default : cry <= ncry & RSTN;
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default: begin eqF <= eqF ; lF <= lF; gF <= gF; end
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|
endcase
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endcase
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if ((state==`fetch) || (state==`ret))
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prefx <= nprefx & RSTN;
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begin
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state <= nstate & {6{RSTN}};
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if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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bF <= bF & RSTN; aF <= naF & RSTN; end
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if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;
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if (dest==3'b011) EBX <= alu_out; else EBX<=EBX;
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bF <= bF & RSTN; aF <= aF & RSTN; end
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if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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case(state) // EAX control
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;
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`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
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end
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`mul2 : EAX <= EBX;
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else if (state==`mul)
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`sml1 : EAX <= smlEAX;
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begin
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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EAX <= {EAX[30:0],1'b0};
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default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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if (EDX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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endcase
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EDX <= {1'b0,EDX[31:1]};
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case(state) // EBX control
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ECX <= ECX; ESP <= ESP; EBP <= EBP;
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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end
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else if (state==`mul2)
|
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begin
|
|
EAX <= EBX; EBX <= EBX; EDX <= EDX;
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ECX <= ECX; ESP <= ESP; EBP <= EBP;
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end
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else
|
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begin
|
|
EBP<=EBP; EAX<=EAX;ECX<=ECX; EDX<=EDX;
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case(state)
|
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call,
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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default : EBX<=EBX;
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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`shift : EBX<={EBX[31:5],EBX_shtr};
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default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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endcase
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case(state) // ECX control
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`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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`sml1 : ECX <= smlECX;
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default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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endcase
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endcase
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case(state)
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if (dest==3'b010) EDX <= alu_out; else EDX<=EDX; // EDX control
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case(state) // ESP control
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`init : ESP<=32'h00ff;
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`call : ESP<=ESP - 4'b0100;
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`call : ESP<=ESP - 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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default: ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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endcase
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endcase
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end
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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case(state)
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case(state) // PC control
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`init : PC<=32'h00;
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`jae2 : PC<=pc_jae;
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`jbe2 : PC<=pc_jbe;
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`ja2 : PC<=pc_ja ;
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`jb2 : PC<=pc_jb ;
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`jge2 : PC<=pc_jge;
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`jge2 : PC<=pc_jge;
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`jle2 : PC<=pc_jle;
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`jle2 : PC<=pc_jle;
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`jg2 : PC<=pc_jg ;
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`jg2 : PC<=pc_jg ;
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`jl2 : PC<=pc_jl ;
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`jl2 : PC<=pc_jl ;
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`je2 : PC<=pc_eq ;
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`je2 : PC<=pc_eq ;
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`jne2 : PC<=pc_neq;
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`jne2 : PC<=pc_neq;
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`jmp2,`call2 : PC<=pc_jp ;
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`jmp2,`call2 : PC<=pc_jp ;
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`ret2 : PC<=D ;
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`ret2 : PC<=D ;
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`mul,`mul2 : PC<=PC ;
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,
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default : PC<=incPC ;
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`shift : PC<=PC ;
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default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
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endcase
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endcase
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end
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end
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// muxing for source selection, used in alu & moves
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// muxing for source selection, used in alu & moves
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always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
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always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
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case(src)
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case(src)
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3'b000 : regsrc = EAX;
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3'b000 : regsrc = EAX;
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3'b001 : regsrc = ECX;
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3'b001 : regsrc = ECX;
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3'b010 : regsrc = EDX;
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3'b010 : regsrc = EDX;
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3'b011 : regsrc = EBX;
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3'b100 : regsrc = ESP;
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3'b100 : regsrc = ESP;
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3'b101 : regsrc = EBP;
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3'b101 : regsrc = EBP;
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3'b111 : regsrc = D;
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3'b111 : regsrc = D;
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default: regsrc = EBX;
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default: regsrc = EBX;
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endcase
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endcase
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| Line 121... |
Line 132... |
always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
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always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
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case(dest)
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case(dest)
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3'b000 : regdest = EAX;
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3'b000 : regdest = EAX;
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3'b001 : regdest = ECX;
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3'b001 : regdest = ECX;
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3'b010 : regdest = EDX;
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3'b010 : regdest = EDX;
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3'b011 : regdest = EBX;
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3'b100 : regdest = ESP;
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3'b100 : regdest = ESP;
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3'b101 : regdest = EBP;
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3'b101 : regdest = EBP;
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3'b111 : regdest = D ;
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3'b111 : regdest = D ;
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default: regdest = EBX;
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default: regdest = EBX;
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endcase
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endcase
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| Line 141... |
Line 151... |
6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation
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6'b001010 : {ncry,alu_out} = sub_out ; // SUB , carry generation
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6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR
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6'b001100 : {ncry,alu_out} = {cry,regdest ^ regsrc}; // XOR
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6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE
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6'b100010 : {ncry,alu_out} = {cry, regsrc}; // MOVE
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6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE
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6'b101101 : {ncry,alu_out} = {cry, Zregsrc}; // MOVE
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6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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6'b101111 : {ncry,alu_out} = {cry, Sregsrc}; // MOVE
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6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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//6'b110000 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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//6'b110100 : {ncry,alu_out} = {cry, sft_out[31:0]}; // SHIFT
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
|
default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
|
endcase
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endcase
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else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
|
else {ncry,alu_out} = {cry,regdest };
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else {ncry,alu_out} = {cry,regdest };
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// Main instruction decode
|
// Main instruction decode
|
always @(ID,state,EDX)
|
always @(ID,state,ECX,EBX_shtr)
|
begin
|
begin
|
// One cycle instructions, operand selection
|
// One cycle instructions, operand selection
|
if (state == `fetch)
|
if ((state == `fetch) || (state ==`shift))
|
begin
|
|
case ({ID[15:14],ID[9],ID[7]})
|
case ({ID[15:14],ID[9],ID[7]})
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4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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4'b1010 : begin src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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4'b1010 : begin src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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4'b1001 : begin src=ID[5:3]; dest=ID[2:0]; end // reg2reg xfer (x89 xC0)
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//4'b1001 : begin src=ID[5:3]; dest=ID[2:0]; end // reg2reg xfer (x89 xC0)
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4'b1011 : begin src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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4'b1011 : begin src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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4'b0001 : begin src=ID[5:3]; dest=ID[2:0]; end // alu op
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//4'b0001 : begin src=ID[5:3]; dest=ID[2:0]; end // alu op
|
4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op
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4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op
|
default : begin src=ID[5:3]; dest=ID[2:0]; end // shift
|
default : begin src=ID[5:3]; dest=ID[2:0]; end // shift
|
endcase
|
endcase
|
end
|
|
else if (state==`ret)
|
else if (state==`ret)
|
begin src = 3'b011; dest = 3'b100; end
|
begin src = 3'b011; dest = 3'b100; end
|
else begin src = 3'b000; dest = 3'b000; end
|
else begin src = 3'b000; dest = 3'b000; end
|
// instructions that require more than one cycle to execute
|
// instructions that require more than one cycle to execute
|
if (state == `fetch)
|
if (state == `fetch)
|
begin
|
begin
|
casex(ID)
|
casex(ID)
|
16'h90e9: nstate = `jmp;
|
16'h90e9: nstate = `jmp;
|
|
16'h0f87: nstate = `ja;
|
|
16'h0f86: nstate = `jbe;
|
|
16'h0f83: nstate = `jae;
|
|
16'h0f82: nstate = `jb;
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16'h0f8f: nstate = `jg;
|
16'h0f8f: nstate = `jg;
|
16'h0f8e: nstate = `jle;
|
16'h0f8e: nstate = `jle;
|
16'h0f8d: nstate = `jge;
|
16'h0f8d: nstate = `jge;
|
16'h0f8c: nstate = `jl;
|
16'h0f8c: nstate = `jl;
|
16'h0f85: nstate = `jne;
|
16'h0f85: nstate = `jne;
|
| Line 181... |
Line 194... |
16'h90bb: nstate = `imm;
|
16'h90bb: nstate = `imm;
|
16'h8d9d: nstate = `lea;
|
16'h8d9d: nstate = `lea;
|
16'h90e8: nstate = `call;
|
16'h90e8: nstate = `call;
|
16'h90c3: nstate = `ret;
|
16'h90c3: nstate = `ret;
|
16'hc1xx: nstate = `shift;
|
16'hc1xx: nstate = `shift;
|
16'hafc2: nstate = `mul;
|
16'hd3xx: nstate = `shift;
|
|
16'hf7e1: nstate = `mul;
|
|
16'hafc1: nstate = `sml1;
|
default : nstate = `fetch;
|
default : nstate = `fetch;
|
endcase
|
endcase
|
if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
|
if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
|
if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
|
if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
nprefx = 1'b0; cmpr = 1'b0;
|
nprefx = 1'b0; cmpr = 1'b0;
|
if((state==`mul)&&!(EDX==32'b0)) nstate=`mul;
|
if((state==`mul)&&!(ECX==32'b0)) nstate=`mul;
|
else if((state==`mul)&& (EDX==32'b0)) nstate=`mul2;
|
else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
|
else if (state==`mul2) nstate = `fetch;
|
else if (state==`mul2) nstate = `fetch;
|
|
else if (state==`sml1) nstate = `sml2;
|
|
else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
|
|
else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
|
|
else if (state==`sml1) nstate = `sml3;
|
else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
|
else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
|
else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
|
else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
|
else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
|
else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
|
else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
|
else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
|
else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
|
else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
|
else if (state==`jle) nstate = `jle2; else if (state==`jle2) nstate = `fetch;
|
else if (state==`jle) nstate = `jle2; else if (state==`jle2) nstate = `fetch;
|
else if (state==`jl ) nstate = `jl2 ; else if (state==`jl2 ) nstate = `fetch;
|
else if (state==`jl ) nstate = `jl2 ; else if (state==`jl2 ) nstate = `fetch;
|
|
else if (state==`jae) nstate = `jae2; else if (state==`jae2) nstate = `fetch;
|
|
else if (state==`ja ) nstate = `ja2 ; else if (state==`ja2 ) nstate = `fetch;
|
|
else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
|
|
else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
|
else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
|
else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
|
else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
|
else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
|
else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if (state==`shift) nstate = `fetch;
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else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
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else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
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else nstate = `fetch;
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else nstate = `fetch;
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end
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end
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end
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end
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign IA = PC ;
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assign IA = PC ;
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assign sft_in = regdest ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign shtr = ID[12] ? ECX[4:0] : EBX[4:0] ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign WEN = (ID[15:8]==8'h90) ? 1'b1 :
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assign WEN = (ID[15:8]==8'h90) ? 1'b1 :
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(state == `call2) ? 1'b0 :
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(state == `call2) ? 1'b0 :
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(dest == 3'b111) ? 1'b0 : 1'b1 ;
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(dest == 3'b111) ? 1'b0 : 1'b1 ;
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assign tst = sft_in >>> (shtr);
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assign sft_out = (src == 3'b111) ? tst : //sar
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(src == 3'b101) ? (sft_in >> shtr ) : //shr
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(sft_in << shtr ) ; //shl
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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{ 24'b0 , regsrc[7:0] } ;
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{ 24'b0 , regsrc[7:0] } ;
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assign BEN = (state == `call2 ) ? 1'b1 :
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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{ prefx , ID[8] } ;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign nlF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign nlF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign ngF = (regsrc < regdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign nbF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign naF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign incPC = PC + 3'b010;
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assign incPC = PC + 3'b010;
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assign pc_jge = ( eqF|gF) ? pc_jp : incPC;
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assign pc_jge = ( eqF|gF) ? pc_jp : incPC;
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assign pc_jle = ( eqF|lF) ? pc_jp : incPC;
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assign pc_jle = ( eqF|lF) ? pc_jp : incPC;
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assign pc_jg = ( gF ) ? pc_jp : incPC;
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assign pc_jg = ( gF ) ? pc_jp : incPC;
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assign pc_jl = ( lF ) ? pc_jp : incPC;
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assign pc_jl = ( lF ) ? pc_jp : incPC;
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assign pc_jae = (eqF|aF) ? pc_jp : incPC;
|
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assign pc_jbe = (eqF|bF) ? pc_jp : incPC;
|
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assign pc_ja = (aF ) ? pc_jp : incPC;
|
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assign pc_jb = (bF ) ? pc_jp : incPC;
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assign pc_eq = ( eqF ) ? pc_jp : incPC;
|
assign pc_eq = ( eqF ) ? pc_jp : incPC;
|
assign pc_neq = ( eqF ) ? incPC : pc_jp;
|
assign pc_neq = ( eqF ) ? incPC : pc_jp;
|
assign pc_jp = incPC+{ID,EBX[15:0]};
|
assign pc_jp = incPC+{ID,EBX[15:0]};
|
|
assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
|
|
(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr
|
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{regdest[30:0],1'b0 } ; //shl
|
assign adder_out= nncry + regsrc + regdest;
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assign adder_out= nncry + regsrc + regdest;
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assign sub_out= regdest - regsrc - nncry;
|
assign sub_out= regdest - regsrc - nncry;
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assign nncry = (ID[12] ? cry : 1'b0);
|
assign nncry = (ID[12] ? cry : 1'b0);
|
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assign EBX_shtr = EBX[4:0] - 1'b1;
|
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assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
|
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assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
|
endmodule
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endmodule
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