| Line 5... |
Line 5... |
output [31:0] A;
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output [31:0] A;
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input [31:0] D;
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input [31:0] D;
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output [31:0] Q;
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output [31:0] Q;
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output WEN;
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output WEN;
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output [1:0] BEN;
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output [1:0] BEN;
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wire nncry,neqF,ngF,nlF,naF,nbF;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [5:0] state,nstate;
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reg [5:0] state,nstate;
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reg [2:0] src,dest;
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reg [2:0] src,dest;
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reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
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| Line 54... |
Line 54... |
`define jae2 6'b100011
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`define jae2 6'b100011
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`define sml1 6'b100100
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`define sml1 6'b100100
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`define sml2 6'b100101
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`define sml2 6'b100101
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`define sml3 6'b100110
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`define sml3 6'b100110
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`define sml4 6'b100111
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`define sml4 6'b100111
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`define sdv1 6'b101000
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`define sdv2 6'b101001
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`define sdv3 6'b101010
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`define sdv4 6'b101011
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`define div1 6'b101100
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`define init 6'b000000
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`define init 6'b000000
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always @(posedge CLK)
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always @(posedge CLK)
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begin
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begin
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case (state) // cry control
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case (state) // cry control
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`sml1 : cry <= EAX[31] ^ ECX[31];
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`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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`div1 : cry <= 1'b0;
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default : cry <= ncry & RSTN;
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default : cry <= ncry & RSTN;
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endcase
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endcase
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prefx <= nprefx & RSTN;
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prefx <= nprefx & RSTN;
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state <= nstate & {6{RSTN}};
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state <= nstate & {6{RSTN}};
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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| Line 72... |
Line 78... |
case(state) // EAX control
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case(state) // EAX control
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`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
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`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
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`mul2 : EAX <= EBX;
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`mul2 : EAX <= EBX;
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`sml1 : EAX <= smlEAX;
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`sml1 : EAX <= smlEAX;
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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`sdv1,`div1 : EAX <= 32'b0;
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`sdv3 : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
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`sdv4 : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
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default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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endcase
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endcase
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case(state) // EBX control
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case(state) // EBX control
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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`shift : EBX<={EBX[31:5],EBX_shtr};
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`shift : EBX<={EBX[31:5],EBX_shtr};
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`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
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`div1 : EBX<={ 2'b00,EBX[29:0]};
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`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
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`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
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default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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endcase
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endcase
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case(state) // ECX control
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case(state) // ECX control
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`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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`sml1 : ECX <= smlECX;
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`sml1,`sdv1 : ECX <= smlECX;
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`div1 : ECX <= ECX;
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`sdv2 : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
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`sdv3 : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
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`sdv4 : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
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default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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endcase
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endcase
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if (dest==3'b010) EDX <= alu_out; else EDX<=EDX; // EDX control
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case(state) // EDX control
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`sdv1 : EDX <= smlEAX;
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`div1 : EDX <= EAX;
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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endcase
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case(state) // ESP control
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case(state) // ESP control
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`init : ESP<=32'h00ff;
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`init : ESP<=32'h00ff;
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`call : ESP<=ESP - 4'b0100;
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`call : ESP<=ESP - 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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| Line 110... |
Line 133... |
`jl2 : PC<=pc_jl ;
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`jl2 : PC<=pc_jl ;
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`je2 : PC<=pc_eq ;
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`je2 : PC<=pc_eq ;
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`jne2 : PC<=pc_neq;
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`jne2 : PC<=pc_neq;
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`jmp2,`call2 : PC<=pc_jp ;
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`jmp2,`call2 : PC<=pc_jp ;
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`ret2 : PC<=D ;
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`ret2 : PC<=D ;
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
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`shift : PC<=PC ;
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`shift : PC<=PC ;
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default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
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default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
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endcase
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endcase
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end
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end
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// muxing for source selection, used in alu & moves
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// muxing for source selection, used in alu & moves
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| Line 158... |
Line 181... |
default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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default : {ncry,alu_out} = {cry,regdest }; // DO NOTHING
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endcase
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endcase
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else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
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else if (state == `shift ) {ncry,alu_out} = {cry,sft_out };
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else {ncry,alu_out} = {cry,regdest };
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else {ncry,alu_out} = {cry,regdest };
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// Main instruction decode
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// Main instruction decode
|
always @(ID,state,ECX,EBX_shtr)
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always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
|
begin
|
begin
|
// One cycle instructions, operand selection
|
// One cycle instructions, operand selection
|
if ((state == `fetch) || (state ==`shift))
|
if ((state == `fetch) || (state ==`shift))
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case ({ID[15:14],ID[9],ID[7]})
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case ({ID[15:14],ID[9],ID[7]})
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4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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| Line 173... |
Line 196... |
4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op
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4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op
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default : begin src=ID[5:3]; dest=ID[2:0]; end // shift
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default : begin src=ID[5:3]; dest=ID[2:0]; end // shift
|
endcase
|
endcase
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else if (state==`ret)
|
else if (state==`ret)
|
begin src = 3'b011; dest = 3'b100; end
|
begin src = 3'b011; dest = 3'b100; end
|
|
else if (state==`sdv3)
|
|
begin src = 3'b001; dest = 3'b010; end
|
else begin src = 3'b000; dest = 3'b000; end
|
else begin src = 3'b000; dest = 3'b000; end
|
// instructions that require more than one cycle to execute
|
// instructions that require more than one cycle to execute
|
if (state == `fetch)
|
if (state == `fetch)
|
begin
|
begin
|
casex(ID)
|
casex(ID)
|
| Line 196... |
Line 221... |
16'h90e8: nstate = `call;
|
16'h90e8: nstate = `call;
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16'h90c3: nstate = `ret;
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16'h90c3: nstate = `ret;
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16'hc1xx: nstate = `shift;
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16'hc1xx: nstate = `shift;
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16'hd3xx: nstate = `shift;
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16'hd3xx: nstate = `shift;
|
16'hf7e1: nstate = `mul;
|
16'hf7e1: nstate = `mul;
|
|
16'hf7f9: nstate = `sdv1;
|
|
16'hf7f1: nstate = `div1;
|
16'hafc1: nstate = `sml1;
|
16'hafc1: nstate = `sml1;
|
default : nstate = `fetch;
|
default : nstate = `fetch;
|
endcase
|
endcase
|
if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
|
if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
|
if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
|
if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
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| Line 211... |
Line 238... |
else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
|
else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
|
else if (state==`mul2) nstate = `fetch;
|
else if (state==`mul2) nstate = `fetch;
|
else if (state==`sml1) nstate = `sml2;
|
else if (state==`sml1) nstate = `sml2;
|
else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
|
else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
|
else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
|
else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
|
else if (state==`sml1) nstate = `sml3;
|
else if (state==`div1) nstate = `sdv2;
|
|
else if (state==`sdv1) nstate = `sdv2;
|
|
else if((state==`sdv2) && (divF1 == 1'b0) ) nstate=`sdv2;
|
|
else if((state==`sdv2) && (divF1 == 1'b1) ) nstate=`sdv3;
|
|
else if((state==`sdv3) && (divF2 == 1'b0) ) nstate=`sdv3;
|
|
else if((state==`sdv3) && (divF2 == 1'b1) ) nstate=`sdv4;
|
else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
|
else if (state==`jmp) nstate = `jmp2; else if (state==`jmp2) nstate = `fetch;
|
else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
|
else if (state==`jne) nstate = `jne2; else if (state==`jne2) nstate = `fetch;
|
else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
|
else if (state==`je ) nstate = `je2 ; else if (state==`je2 ) nstate = `fetch;
|
else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
|
else if (state==`jge) nstate = `jge2; else if (state==`jge2) nstate = `fetch;
|
else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
|
else if (state==`jg ) nstate = `jg2 ; else if (state==`jg2 ) nstate = `fetch;
|
| Line 271... |
Line 303... |
assign sub_out= regdest - regsrc - nncry;
|
assign sub_out= regdest - regsrc - nncry;
|
assign nncry = (ID[12] ? cry : 1'b0);
|
assign nncry = (ID[12] ? cry : 1'b0);
|
assign EBX_shtr = EBX[4:0] - 1'b1;
|
assign EBX_shtr = EBX[4:0] - 1'b1;
|
assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
|
assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
|
assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
|
assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
|
|
assign divF1 = ({ECX[30:0],1'b0} > EDX) ? 1'b1 : 1'b0;
|
|
assign divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
|
endmodule
|
endmodule
|
|
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No newline at end of file
|
No newline at end of file
|
