OpenCores
URL https://opencores.org/ocsvn/sub86/sub86/trunk

Subversion Repositories sub86

[/] [sub86/] [trunk/] [sub86.v] - Diff between revs 5 and 6

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 5 Rev 6
Line 5... Line 5...
output [31:0] A;
output [31:0] A;
input  [31:0] D;
input  [31:0] D;
output [31:0] Q;
output [31:0] Q;
output        WEN;
output        WEN;
output  [1:0] BEN;
output  [1:0] BEN;
wire          nncry,neqF,ngF,nlF,naF,nbF;
wire          nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg    [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
reg     [5:0] state,nstate;
reg     [5:0] state,nstate;
reg     [2:0] src,dest;
reg     [2:0] src,dest;
reg           cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
reg           cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
wire   [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
Line 54... Line 54...
`define jae2  6'b100011
`define jae2  6'b100011
`define sml1  6'b100100
`define sml1  6'b100100
`define sml2  6'b100101
`define sml2  6'b100101
`define sml3  6'b100110
`define sml3  6'b100110
`define sml4  6'b100111
`define sml4  6'b100111
 
`define sdv1  6'b101000
 
`define sdv2  6'b101001
 
`define sdv3  6'b101010
 
`define sdv4  6'b101011
 
`define div1  6'b101100
`define init  6'b000000
`define init  6'b000000
 always @(posedge CLK)
 always @(posedge CLK)
     begin
     begin
      case (state) // cry control
      case (state) // cry control
         `sml1     : cry <= EAX[31] ^ ECX[31];
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
 
         `div1      : cry <= 1'b0;
         default   : cry <= ncry & RSTN;
         default   : cry <= ncry & RSTN;
      endcase
      endcase
      prefx <= nprefx & RSTN;
      prefx <= nprefx & RSTN;
      state <= nstate & {6{RSTN}};
      state <= nstate & {6{RSTN}};
      if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
      if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
Line 72... Line 78...
      case(state)  // EAX control
      case(state)  // EAX control
        `mul,`sml2  : EAX <= {EAX[30:0],1'b0};
        `mul,`sml2  : EAX <= {EAX[30:0],1'b0};
        `mul2       : EAX <= EBX;
        `mul2       : EAX <= EBX;
        `sml1       : EAX <= smlEAX;
        `sml1       : EAX <= smlEAX;
        `sml3       : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
        `sml3       : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
 
        `sdv1,`div1 : EAX <= 32'b0;
 
        `sdv3       : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
 
        `sdv4       : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
        default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
        default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
      endcase
      endcase
      case(state)  // EBX control
      case(state)  // EBX control
        `jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
        `jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
        `lea        : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
        `lea        : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
        `imm2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
        `imm2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
        `lea2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
        `lea2       : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
        `mul,`sml2  : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
        `mul,`sml2  : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
        `shift      : EBX<={EBX[31:5],EBX_shtr};
        `shift      : EBX<={EBX[31:5],EBX_shtr};
 
        `sdv1       : EBX<={EAX[31],ECX[31],EBX[29:0]};
 
        `div1       : EBX<={          2'b00,EBX[29:0]};
 
        `sdv2       : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
 
        `sdv3       : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
        default     : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
        default     : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
      endcase
      endcase
      case(state)  // ECX control
      case(state)  // ECX control
        `mul,`sml2  : ECX <= {1'b0,ECX[31:1]};
        `mul,`sml2  : ECX <= {1'b0,ECX[31:1]};
        `sml1       : ECX <= smlECX;
        `sml1,`sdv1 : ECX <= smlECX;
 
        `div1       : ECX <= ECX;
 
        `sdv2       : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
 
        `sdv3       : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
 
        `sdv4       : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
        default     : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
        default     : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
      endcase
      endcase
      if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;  // EDX control       
      case(state)  // EDX control
 
        `sdv1       : EDX <= smlEAX;
 
        `div1       : EDX <=    EAX;
 
        `sdv3       : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
 
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
 
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
 
      endcase
      case(state)  // ESP control
      case(state)  // ESP control
        `init       : ESP<=32'h00ff;
        `init       : ESP<=32'h00ff;
        `call       : ESP<=ESP - 4'b0100;
        `call       : ESP<=ESP - 4'b0100;
        `ret2       : ESP<=ESP + 4'b0100;
        `ret2       : ESP<=ESP + 4'b0100;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
Line 110... Line 133...
       `jl2         : PC<=pc_jl ;
       `jl2         : PC<=pc_jl ;
       `je2         : PC<=pc_eq ;
       `je2         : PC<=pc_eq ;
       `jne2        : PC<=pc_neq;
       `jne2        : PC<=pc_neq;
       `jmp2,`call2 : PC<=pc_jp ;
       `jmp2,`call2 : PC<=pc_jp ;
       `ret2        : PC<=D     ;
       `ret2        : PC<=D     ;
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `shift       : PC<=PC    ;
       `shift       : PC<=PC    ;
       default      : if (nstate == `shift) PC<=PC; else PC<=incPC ;
       default      : if (nstate == `shift) PC<=PC; else PC<=incPC ;
      endcase
      endcase
     end
     end
// muxing for source selection, used in alu & moves
// muxing for source selection, used in alu & moves
Line 158... Line 181...
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
   default   : {ncry,alu_out} = {cry,regdest         };  // DO NOTHING
  endcase
  endcase
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else if (state == `shift ) {ncry,alu_out} = {cry,sft_out           };
  else {ncry,alu_out} = {cry,regdest         };
  else {ncry,alu_out} = {cry,regdest         };
// Main instruction decode
// Main instruction decode
always @(ID,state,ECX,EBX_shtr)
always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
 begin
 begin
   // One cycle instructions, operand selection
   // One cycle instructions, operand selection
   if ((state == `fetch) || (state ==`shift))
   if ((state == `fetch) || (state ==`shift))
     case ({ID[15:14],ID[9],ID[7]})
     case ({ID[15:14],ID[9],ID[7]})
      4'b1000  : begin src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
      4'b1000  : begin src=ID[5:3]; dest= 3'b111; end  // store into ram (x89 x00)
Line 173... Line 196...
      4'b0011  : begin src=ID[2:0]; dest=ID[5:3]; end  // alu op
      4'b0011  : begin src=ID[2:0]; dest=ID[5:3]; end  // alu op
      default  : begin src=ID[5:3]; dest=ID[2:0]; end  // shift
      default  : begin src=ID[5:3]; dest=ID[2:0]; end  // shift
     endcase
     endcase
   else if (state==`ret)
   else if (state==`ret)
        begin src = 3'b011; dest = 3'b100; end
        begin src = 3'b011; dest = 3'b100; end
 
   else if (state==`sdv3)
 
        begin src = 3'b001; dest = 3'b010; end
   else begin src = 3'b000; dest = 3'b000; end
   else begin src = 3'b000; dest = 3'b000; end
   // instructions that require more than one cycle to execute
   // instructions that require more than one cycle to execute
   if (state == `fetch)
   if (state == `fetch)
   begin
   begin
    casex(ID)
    casex(ID)
Line 196... Line 221...
     16'h90e8: nstate = `call;
     16'h90e8: nstate = `call;
     16'h90c3: nstate = `ret;
     16'h90c3: nstate = `ret;
     16'hc1xx: nstate = `shift;
     16'hc1xx: nstate = `shift;
     16'hd3xx: nstate = `shift;
     16'hd3xx: nstate = `shift;
     16'hf7e1: nstate = `mul;
     16'hf7e1: nstate = `mul;
 
     16'hf7f9: nstate = `sdv1;
 
     16'hf7f1: nstate = `div1;
     16'hafc1: nstate = `sml1;
     16'hafc1: nstate = `sml1;
     default : nstate = `fetch;
     default : nstate = `fetch;
    endcase
    endcase
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
Line 211... Line 238...
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if((state==`mul)&& (ECX==32'b0)) nstate=`mul2;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`mul2)  nstate = `fetch;
   else if (state==`sml1)  nstate = `sml2;
   else if (state==`sml1)  nstate = `sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&&!(ECX==32'b0)) nstate=`sml2;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
   else if((state==`sml2)&& (ECX==32'b0)) nstate=`sml3;
   else if (state==`sml1)  nstate = `sml3;
   else if (state==`div1)  nstate = `sdv2;
 
   else if (state==`sdv1)  nstate = `sdv2;
 
   else if((state==`sdv2) && (divF1 == 1'b0) ) nstate=`sdv2;
 
   else if((state==`sdv2) && (divF1 == 1'b1) ) nstate=`sdv3;
 
   else if((state==`sdv3) && (divF2 == 1'b0) ) nstate=`sdv3;
 
   else if((state==`sdv3) && (divF2 == 1'b1) ) nstate=`sdv4;
   else if (state==`jmp)   nstate = `jmp2;  else if (state==`jmp2)  nstate = `fetch;
   else if (state==`jmp)   nstate = `jmp2;  else if (state==`jmp2)  nstate = `fetch;
   else if (state==`jne)   nstate = `jne2;  else if (state==`jne2)  nstate = `fetch;
   else if (state==`jne)   nstate = `jne2;  else if (state==`jne2)  nstate = `fetch;
   else if (state==`je )   nstate = `je2 ;  else if (state==`je2 )  nstate = `fetch;
   else if (state==`je )   nstate = `je2 ;  else if (state==`je2 )  nstate = `fetch;
   else if (state==`jge)   nstate = `jge2;  else if (state==`jge2)  nstate = `fetch;
   else if (state==`jge)   nstate = `jge2;  else if (state==`jge2)  nstate = `fetch;
   else if (state==`jg )   nstate = `jg2 ;  else if (state==`jg2 )  nstate = `fetch;
   else if (state==`jg )   nstate = `jg2 ;  else if (state==`jg2 )  nstate = `fetch;
Line 271... Line 303...
assign   sub_out= regdest - regsrc - nncry;
assign   sub_out= regdest - regsrc - nncry;
assign    nncry = (ID[12] ? cry : 1'b0);
assign    nncry = (ID[12] ? cry : 1'b0);
assign EBX_shtr = EBX[4:0] - 1'b1;
assign EBX_shtr = EBX[4:0] - 1'b1;
assign smlEAX   = EAX[31] ? ((~EAX) + 1) : EAX;
assign smlEAX   = EAX[31] ? ((~EAX) + 1) : EAX;
assign smlECX   = ECX[31] ? ((~ECX) + 1) : ECX;
assign smlECX   = ECX[31] ? ((~ECX) + 1) : ECX;
 
assign    divF1 = ({ECX[30:0],1'b0}  > EDX) ? 1'b1 : 1'b0;
 
assign    divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.