| Line 1... |
Line 1... |
module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN );
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module sub86( CLK, RSTN, IA, ID, A, D, Q, WEN,BEN,CE,RD );
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input CLK,RSTN;
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input CLK,RSTN,CE;
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output [31:0] IA;
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output [31:0] IA;
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input [15:0] ID;
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input [15:0] ID;
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output [31:0] A;
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output [31:0] A;
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input [31:0] D;
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input [31:0] D;
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output [31:0] Q;
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output [31:0] Q;
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output WEN;
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output WEN;
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output RD;
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output [1:0] BEN;
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output [1:0] BEN;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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wire nncry,neqF,ngF,nlF,naF,nbF,divF1,divF2;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [31:0] EAX,EBX,ECX,EDX,EBP,ESP,PC,regsrc,regdest,alu_out;
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reg [5:0] state,nstate;
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reg [5:0] state,nstate;
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reg [2:0] src,dest;
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reg [2:0] src,dest;
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reg cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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reg RD,cry,ncry,prefx,nprefx,cmpr,eqF,gF,lF,aF,bF;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq;
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wire [31:0] pc_ja,pc_jae,pc_jb,pc_jbe,pc_jg,pc_jge,pc_jl,pc_jle,pc_eq,pc_jp,pc_neq,pc_sh;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [31:0] Sregsrc,Zregsrc,incPC,sft_out,smlEAX,smlECX;
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wire [32:0] adder_out,sub_out;
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wire [32:0] adder_out,sub_out;
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wire [4:0] EBX_shtr;
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wire [4:0] EBX_shtr;
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wire signed [31:0] ssregsrc, ssregdest;
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wire signed [31:0] ssregsrc, ssregdest;
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`define fetch 6'b111111
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`define fetch 6'b111111
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Line 60... |
`define sdv1 6'b101000
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`define sdv1 6'b101000
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`define sdv2 6'b101001
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`define sdv2 6'b101001
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`define sdv3 6'b101010
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`define sdv3 6'b101010
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`define sdv4 6'b101011
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`define sdv4 6'b101011
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`define div1 6'b101100
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`define div1 6'b101100
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`define leas 6'b101101
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`define init 6'b000000
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`define init 6'b000000
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always @(posedge CLK)
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always @(posedge CLK)
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if ((CE ==1'b1) || (RSTN ==1'b0))
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begin
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begin
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case (state) // cry control
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case (state) // cry control
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`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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`div1 : cry <= 1'b0;
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`div1 : cry <= 1'b0;
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default : cry <= ncry & RSTN;
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default : cry <= ncry & RSTN;
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endcase
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endcase
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prefx <= nprefx & RSTN;
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prefx <= nprefx & RSTN;
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state <= nstate & {6{RSTN}};
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state <= nstate & {6{RSTN}};
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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if (cmpr) begin eqF <= neqF & RSTN; lF <= nlF & RSTN; gF <= ngF & RSTN;
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bF <= bF & RSTN; aF <= naF & RSTN; end
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bF <= nbF & RSTN; aF <= naF & RSTN; end
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else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;
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else begin eqF <= eqF & RSTN; lF <= lF & RSTN; gF <= gF & RSTN;
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bF <= bF & RSTN; aF <= aF & RSTN; end
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bF <= bF & RSTN; aF <= aF & RSTN; end
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case(state) // EAX control
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case(state) // EAX control
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`init : EAX <= 32'b0;
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`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
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`mul,`sml2 : EAX <= {EAX[30:0],1'b0};
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`mul2 : EAX <= EBX;
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`mul2 : EAX <= EBX;
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`sml1 : EAX <= smlEAX;
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`sml1 : EAX <= smlEAX;
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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`sml3 : if (cry==1'b0) EAX <= EBX; else EAX <= ((~EBX) + 1'b1);
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`sdv1,`div1 : EAX <= 32'b0;
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`sdv1,`div1 : EAX <= 32'b0;
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`sdv3 : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
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`sdv3 : if (nlF==1'b0) EAX <= EAX + ( 1 << EBX_shtr); else EAX <=EAX;
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`sdv4 : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
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`sdv4 : if (cry==1'b1) EAX <= ((~EAX) + 1'b1); else EAX <= EAX;
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default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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default: if (dest==3'b000) EAX <= alu_out; else EAX<=EAX;
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endcase
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endcase
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case(state) // EBX control
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case(state) // EBX control
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`init : EBX <= 32'b0;
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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`jmp , `jg, `jge , `jl, `jle, `je, `jne, `imm, `call, `jb,`jbe,`ja,`jae,
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`lea : EBX<={EBX[31:16],ID[7:0],ID[15:8]};
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`leas : EBX<={ {24{ID[15]}} , ID[15:8]}+EBP;
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`imm2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]};
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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`lea2 : EBX<={ID[7:0],ID[15:8], EBX[15:0]}+EBP;
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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`mul,`sml2 : if (ECX[0] == 1'b1) EBX <= EAX+EBX; else EBX <= EBX;
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`shift : EBX<={EBX[31:5],EBX_shtr};
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`shift : EBX<={EBX[31:5],EBX_shtr};
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`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
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`sdv1 : EBX<={EAX[31],ECX[31],EBX[29:0]};
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`div1 : EBX<={ 2'b00,EBX[29:0]};
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`div1 : EBX<={ 2'b00,EBX[29:0]};
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`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
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`sdv2 : if (divF1==1'b0 ) EBX <= {EBX[31:5],(EBX[4:0]+1'b1)}; else EBX <= EBX;
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`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
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`sdv3 : if (divF1==1'b1 ) EBX <= {EBX[31:5],EBX_shtr}; else EBX <= EBX;
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default : if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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default : if (ID[15:8] == 8'hb3) EBX<= {EBX[31:24],ID[7:0]};
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else if (dest==3'b011) EBX <= alu_out; else EBX <= EBX;
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endcase
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endcase
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case(state) // ECX control
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case(state) // ECX control
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`init : ECX <= 32'b0;
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`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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`mul,`sml2 : ECX <= {1'b0,ECX[31:1]};
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`sml1,`sdv1 : ECX <= smlECX;
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`sml1,`sdv1 : ECX <= smlECX;
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`div1 : ECX <= ECX;
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`div1 : ECX <= ECX;
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`sdv2 : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
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`sdv2 : if (divF1==1'b0 ) ECX <= {ECX[30:0],1'b0}; else ECX<=ECX;
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`sdv3 : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
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`sdv3 : if((divF1==1'b1 ) && (divF2==1'b0)) ECX <= {1'b0,ECX[31:1]}; else ECX<=ECX;
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`sdv4 : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
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`sdv4 : if (EBX[30] == 1'b1) ECX <= ((~ECX) + 1); else ECX<=ECX;
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default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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default : if (dest==3'b001) ECX <= alu_out; else ECX<=ECX;
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endcase
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endcase
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case(state) // EDX control
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case(state) // EDX control
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`init : EDX <= 32'b0;
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`sdv1 : EDX <= smlEAX;
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`sdv1 : EDX <= smlEAX;
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`div1 : EDX <= EAX;
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`div1 : EDX <= EAX;
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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endcase
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endcase
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case(state) // ESP control
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case(state) // ESP control
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`init : ESP<=32'h00ff;
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`init : ESP <= 32'hfffe01ff;
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`call : ESP<=ESP - 4'b0100;
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`call : ESP<=ESP - 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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`ret2 : ESP<=ESP + 4'b0100;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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endcase
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endcase
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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| Line 135... |
Line 144... |
`jne2 : PC<=pc_neq;
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`jne2 : PC<=pc_neq;
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`jmp2,`call2 : PC<=pc_jp ;
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`jmp2,`call2 : PC<=pc_jp ;
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`ret2 : PC<=D ;
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`ret2 : PC<=D ;
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
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`shift : PC<=PC ;
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`shift : PC<=PC ;
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default : if (nstate == `shift) PC<=PC; else PC<=incPC ;
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default : if (nstate == `shift) PC<=PC;
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else if (ID[15:8]==8'heb) PC <= pc_sh;
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else if((ID[15:8]==8'h75) && (eqF==1'b0)) PC <= pc_sh;
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else if((ID[15:8]==8'h74) && (eqF==1'b1)) PC <= pc_sh;
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else PC<=incPC ;
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endcase
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endcase
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end
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end
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// muxing for source selection, used in alu & moves
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// muxing for source selection, used in alu & moves
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always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
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always@(src,EAX,ECX,EDX,EBX,ESP,EBP,D)
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case(src)
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case(src)
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3'b000 : regsrc = EAX;
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3'b000 : regsrc = EAX;
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3'b001 : regsrc = ECX;
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3'b001 : regsrc = ECX;
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3'b010 : regsrc = EDX;
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3'b010 : regsrc = EDX;
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3'b100 : regsrc = ESP;
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3'b100 : regsrc = ESP;
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3'b101 : regsrc = EBP;
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3'b101 : regsrc = EBP;
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3'b110 : regsrc = 32'h04;
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3'b111 : regsrc = D;
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3'b111 : regsrc = D;
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default: regsrc = EBX;
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default: regsrc = EBX;
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endcase
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endcase
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// muxing for 2nd operand selection, used in alu only
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// muxing for 2nd operand selection, used in alu only
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always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
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always@(dest,EAX,ECX,EDX,EBX,ESP,EBP,D)
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| Line 157... |
Line 171... |
3'b000 : regdest = EAX;
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3'b000 : regdest = EAX;
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3'b001 : regdest = ECX;
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3'b001 : regdest = ECX;
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3'b010 : regdest = EDX;
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3'b010 : regdest = EDX;
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3'b100 : regdest = ESP;
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3'b100 : regdest = ESP;
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3'b101 : regdest = EBP;
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3'b101 : regdest = EBP;
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3'b110 : regdest = 32'h04;
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3'b111 : regdest = D ;
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3'b111 : regdest = D ;
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default: regdest = EBX;
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default: regdest = EBX;
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endcase
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endcase
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// alu
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// alu
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always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
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always@(state,regdest,regsrc,ID,cry,Zregsrc,Sregsrc,sft_out,adder_out,sub_out)
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| Line 185... |
Line 200... |
// Main instruction decode
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// Main instruction decode
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always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
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always @(ID,state,ECX,EBX_shtr,EAX,divF1,divF2)
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begin
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begin
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// One cycle instructions, operand selection
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// One cycle instructions, operand selection
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if ((state == `fetch) || (state ==`shift))
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if ((state == `fetch) || (state ==`shift))
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case ({ID[15:14],ID[9],ID[7]})
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casex ({ID[15:14],ID[13],ID[9],ID[7]})
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4'b1000 : begin src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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5'b10x00 : begin RD=0; src=ID[5:3]; dest= 3'b111; end // store into ram (x89 x00)
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4'b1010 : begin src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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5'b10010 : begin RD=1; src= 3'b111; dest=ID[5:3]; end // load from ram (x8b x00)
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//4'b1001 : begin src=ID[5:3]; dest=ID[2:0]; end // reg2reg xfer (x89 xC0)
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5'b10110 : begin RD=0; src= 3'b111; dest=ID[5:3]; end // load bl with immediate
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4'b1011 : begin src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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5'b10x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // reg2reg xfer (x8b xC0)
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//4'b0001 : begin src=ID[5:3]; dest=ID[2:0]; end // alu op
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5'b00x11 : begin RD=0; src=ID[2:0]; dest=ID[5:3]; end // alu op
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4'b0011 : begin src=ID[2:0]; dest=ID[5:3]; end // alu op
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default : begin RD=0; src=ID[5:3]; dest=ID[2:0]; end // shift
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default : begin src=ID[5:3]; dest=ID[2:0]; end // shift
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endcase
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endcase
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else if (state==`ret)
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else if (state==`ret)
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begin src = 3'b011; dest = 3'b100; end
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begin src = 3'b011; dest = 3'b100; RD=0; end
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else if (state==`sdv3)
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else if (state==`sdv3)
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begin src = 3'b001; dest = 3'b010; end
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begin src = 3'b001; dest = 3'b010; RD=0; end
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else begin src = 3'b000; dest = 3'b000; end
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else begin src = 3'b000; dest = 3'b000; RD=0; end
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// instructions that require more than one cycle to execute
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// instructions that require more than one cycle to execute
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if (state == `fetch)
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if (state == `fetch)
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begin
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begin
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casex(ID)
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casex(ID)
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16'h90e9: nstate = `jmp;
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16'h90e9: nstate = `jmp;
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| Line 216... |
Line 230... |
16'h0f8c: nstate = `jl;
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16'h0f8c: nstate = `jl;
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16'h0f85: nstate = `jne;
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16'h0f85: nstate = `jne;
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16'h0f84: nstate = `je;
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16'h0f84: nstate = `je;
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16'h90bb: nstate = `imm;
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16'h90bb: nstate = `imm;
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16'h8d9d: nstate = `lea;
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16'h8d9d: nstate = `lea;
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16'h8d5d: nstate = `leas;
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16'h90e8: nstate = `call;
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16'h90e8: nstate = `call;
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16'h90c3: nstate = `ret;
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16'h90c3: nstate = `ret;
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16'hc1xx: nstate = `shift;
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16'hc1xx: nstate = `shift;
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16'hd3xx: nstate = `shift;
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16'hd3xx: nstate = `shift;
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16'hf7e1: nstate = `mul;
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16'hf7e1: nstate = `mul;
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| Line 269... |
Line 284... |
assign ssregsrc = regsrc;
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign ssregdest= regdest;
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assign IA = PC ;
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assign IA = PC ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign WEN = (ID[15:8]==8'h90) ? 1'b1 :
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assign WEN = (CE == 1'b0) ? 1'b1 :
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(state == `call2) ? 1'b0 :
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({ID[15:9],ID[7]}==8'h88)? 1'b0 :
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(dest == 3'b111) ? 1'b0 : 1'b1 ;
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(state == `call2) ? 1'b0 : 1'b1 ;
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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{ 24'b0 , regsrc[7:0] } ;
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{ 24'b0 , regsrc[7:0] } ;
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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| Line 294... |
Line 309... |
assign pc_ja = (aF ) ? pc_jp : incPC;
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assign pc_ja = (aF ) ? pc_jp : incPC;
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assign pc_jb = (bF ) ? pc_jp : incPC;
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assign pc_jb = (bF ) ? pc_jp : incPC;
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assign pc_eq = (eqF ) ? pc_jp : incPC;
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assign pc_eq = (eqF ) ? pc_jp : incPC;
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assign pc_neq = (eqF ) ? incPC : pc_jp;
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assign pc_neq = (eqF ) ? incPC : pc_jp;
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assign pc_jp = incPC+{ID,EBX[15:0]};
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assign pc_jp = incPC+{ID,EBX[15:0]};
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assign pc_sh = incPC + { {24{ID[7]}} , ID[7:0] };
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assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
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assign sft_out = (src == 3'b111) ? {regdest[31],regdest[31:1]} : //sar
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(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr
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(src == 3'b101) ? { 1'b0,regdest[31:1]} : //shr
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{regdest[30:0],1'b0 } ; //shl
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{regdest[30:0],1'b0 } ; //shl
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assign adder_out= nncry + regsrc + regdest;
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assign adder_out= nncry + regsrc + regdest;
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assign sub_out= regdest - regsrc - nncry;
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assign sub_out= regdest - regsrc - nncry;
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