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[/] [sub86/] [trunk/] [sub86.v] - Diff between revs 7 and 8

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Rev 7 Rev 8
Line 61... Line 61...
`define sdv2  6'b101001
`define sdv2  6'b101001
`define sdv3  6'b101010
`define sdv3  6'b101010
`define sdv4  6'b101011
`define sdv4  6'b101011
`define div1  6'b101100
`define div1  6'b101100
`define leas  6'b101101
`define leas  6'b101101
 
`define calla 6'b101110
 
`define calla2 6'b101111
`define init  6'b000000
`define init  6'b000000
 
 
 always @(posedge CLK)
 always @(posedge CLK)
   if ((CE ==1'b1) || (RSTN ==1'b0))
   if ((CE ==1'b1) || (RSTN ==1'b0))
     begin
     begin
      case (state) // cry control
      case (state) // cry control
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
         `sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
Line 122... Line 125...
        `sdv3       : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
        `sdv3       : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
        `sdv4       : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
        default     : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
      endcase
      endcase
      case(state)  // ESP control
      case(state)  // ESP control
        `init       : ESP <= 32'hfffe01ff;
        `init       : ESP <= 32'h01ff00;
        `call       : ESP <= ESP - 4'b0100;
        `call,`calla: ESP <= ESP - 4'b0100;
        `ret2       : ESP <= ESP + 4'b0100;
        `ret2       : ESP <= ESP + 4'b0100;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
       default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
      endcase
      endcase
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      if (dest==3'b101) EBP <= alu_out; else EBP<=EBP;  // EBP control 
      case(state)  // PC control
      case(state)  // PC control
Line 141... Line 144...
       `jg2         : PC<=pc_jg ;
       `jg2         : PC<=pc_jg ;
       `jl2         : PC<=pc_jl ;
       `jl2         : PC<=pc_jl ;
       `je2         : PC<=pc_eq ;
       `je2         : PC<=pc_eq ;
       `jne2        : PC<=pc_neq;
       `jne2        : PC<=pc_neq;
       `jmp2,`call2 : PC<=pc_jp ;
       `jmp2,`call2 : PC<=pc_jp ;
 
       `calla2      : PC<=EBX;
       `ret2        : PC<=D     ;
       `ret2        : PC<=D     ;
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
       `shift       : PC<=PC    ;
       `shift       : PC<=PC    ;
       default      : if (nstate == `shift) PC<=PC;
       default      : if (nstate == `shift) PC<=PC;
                 else if (ID[15:8]==8'heb) PC <= pc_sh;
                 else if (ID[15:8]==8'heb) PC <= pc_sh;
Line 239... Line 243...
     16'hd3xx: nstate = `shift;
     16'hd3xx: nstate = `shift;
     16'hf7e1: nstate = `mul;
     16'hf7e1: nstate = `mul;
     16'hf7f9: nstate = `sdv1;
     16'hf7f9: nstate = `sdv1;
     16'hf7f1: nstate = `div1;
     16'hf7f1: nstate = `div1;
     16'hafc1: nstate = `sml1;
     16'hafc1: nstate = `sml1;
 
     16'hffd3: nstate = `calla;
     default : nstate = `fetch;
     default : nstate = `fetch;
    endcase
    endcase
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID       == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
    if (ID[15:8] ==  8'h39  ) cmpr   = 1'b1; else cmpr   = 1'b0;
   end
   end
Line 273... Line 278...
   else if (state==`jbe)   nstate = `jbe2;  else if (state==`jbe2)  nstate = `fetch;
   else if (state==`jbe)   nstate = `jbe2;  else if (state==`jbe2)  nstate = `fetch;
   else if (state==`jb )   nstate = `jb2 ;  else if (state==`jb2 )  nstate = `fetch;
   else if (state==`jb )   nstate = `jb2 ;  else if (state==`jb2 )  nstate = `fetch;
   else if (state==`imm)   nstate = `imm2;  else if (state==`imm2)  nstate = `fetch;
   else if (state==`imm)   nstate = `imm2;  else if (state==`imm2)  nstate = `fetch;
   else if (state==`lea)   nstate = `lea2;  else if (state==`lea2)  nstate = `fetch;
   else if (state==`lea)   nstate = `lea2;  else if (state==`lea2)  nstate = `fetch;
   else if (state==`call)  nstate = `call2; else if (state==`call2) nstate = `fetch;
   else if (state==`call)  nstate = `call2; else if (state==`call2) nstate = `fetch;
 
   else if (state==`calla) nstate = `calla2;else if (state==`calla2)nstate = `fetch;
   else if (state==`ret)   nstate = `ret2;  else if (state==`ret2)  nstate = `fetch;
   else if (state==`ret)   nstate = `ret2;  else if (state==`ret2)  nstate = `fetch;
   else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
   else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
   else                    nstate = `fetch;
   else                    nstate = `fetch;
   end
   end
 end
 end
assign ssregsrc = regsrc;
assign ssregsrc = regsrc;
assign ssregdest= regdest;
assign ssregdest= regdest;
assign  IA      = PC                ;
assign  IA      = PC                ;
assign  A       = (state == `call2) ?  ESP          : EBX      ;
assign  A       =((state == `call2)|(state == `calla2)) ?  ESP          : EBX      ;
assign  Q       = (state == `call2) ?  incPC        : regsrc   ;
assign  Q       =((state == `call2)|(state == `calla2)) ?  incPC        : regsrc   ;
assign  WEN     = (CE    ==   1'b0) ?  1'b1         :
assign  WEN     = (CE    ==   1'b0) ?  1'b1         :
                  ({ID[15:9],ID[7]}==8'h88)?  1'b0  :
                  ({ID[15:9],ID[7]}==8'h88)?  1'b0  :
                  (state == `call2) ?  1'b0         : 1'b1     ;
                  (state == `call2) ?  1'b0         :
 
                  (state == `calla2)?  1'b0         : 1'b1     ;
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
assign  Sregsrc =       ID[8]       ? { {16{regsrc[15]}} , regsrc[15:0] } :
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
                                      { {24{regsrc[7] }} , regsrc[7:0]  } ;
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
assign  Zregsrc =       ID[8]       ? {  16'b0           , regsrc[15:0] } :
                                      {  24'b0           , regsrc[7:0]  } ;
                                      {  24'b0           , regsrc[7:0]  } ;
assign      BEN = (state == `call2 )  ? 1'b1 : { prefx   , ID[8]        } ;
assign      BEN = (state == `call2 )  ? 1'b1 : { prefx   , ID[8]        } ;
assign     neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
assign     neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
assign      nlF = (regsrc  > regdest) ? 1'b1 : 1'b0;
assign      nbF = (regsrc  > regdest) ? 1'b1 : 1'b0;
assign      ngF = ~(nlF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign      naF = ~(nlF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign      nbF = (ssregsrc  > ssregdest) ? 1'b1 : 1'b0;
assign      nlF = (ssregsrc  > ssregdest) ? 1'b1 : 1'b0;
assign      naF = ~(nbF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign      ngF = ~(nbF | neqF );// (regsrc  < regdest) ? 1'b1 : 1'b0;
assign    incPC = PC + 3'b010;
assign    incPC = PC + 3'b010;
assign   pc_jge = (eqF|gF) ? pc_jp : incPC;
assign   pc_jge = (eqF|gF) ? pc_jp : incPC;
assign   pc_jle = (eqF|lF) ? pc_jp : incPC;
assign   pc_jle = (eqF|lF) ? pc_jp : incPC;
assign   pc_jg  = (gF    ) ? pc_jp : incPC;
assign   pc_jg  = (gF    ) ? pc_jp : incPC;
assign   pc_jl  = (lF    ) ? pc_jp : incPC;
assign   pc_jl  = (lF    ) ? pc_jp : incPC;

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