| Line 61... |
Line 61... |
`define sdv2 6'b101001
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`define sdv2 6'b101001
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`define sdv3 6'b101010
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`define sdv3 6'b101010
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`define sdv4 6'b101011
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`define sdv4 6'b101011
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`define div1 6'b101100
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`define div1 6'b101100
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`define leas 6'b101101
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`define leas 6'b101101
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`define calla 6'b101110
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`define calla2 6'b101111
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`define init 6'b000000
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`define init 6'b000000
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always @(posedge CLK)
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always @(posedge CLK)
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if ((CE ==1'b1) || (RSTN ==1'b0))
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if ((CE ==1'b1) || (RSTN ==1'b0))
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begin
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begin
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case (state) // cry control
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case (state) // cry control
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`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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`sml1,`sdv1: cry <= EAX[31] ^ ECX[31];
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| Line 122... |
Line 125... |
`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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endcase
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endcase
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case(state) // ESP control
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case(state) // ESP control
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`init : ESP <= 32'hfffe01ff;
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`init : ESP <= 32'h01ff00;
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`call : ESP <= ESP - 4'b0100;
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`call,`calla: ESP <= ESP - 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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endcase
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endcase
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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case(state) // PC control
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case(state) // PC control
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Line 144... |
`jg2 : PC<=pc_jg ;
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`jg2 : PC<=pc_jg ;
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`jl2 : PC<=pc_jl ;
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`jl2 : PC<=pc_jl ;
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`je2 : PC<=pc_eq ;
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`je2 : PC<=pc_eq ;
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`jne2 : PC<=pc_neq;
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`jne2 : PC<=pc_neq;
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`jmp2,`call2 : PC<=pc_jp ;
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`jmp2,`call2 : PC<=pc_jp ;
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`calla2 : PC<=EBX;
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`ret2 : PC<=D ;
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`ret2 : PC<=D ;
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
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`mul,`mul2,`sml1,`sml2,`sml3,`sml4,`sdv1,`sdv2,`sdv3,`sdv4,`div1,
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`shift : PC<=PC ;
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`shift : PC<=PC ;
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default : if (nstate == `shift) PC<=PC;
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default : if (nstate == `shift) PC<=PC;
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else if (ID[15:8]==8'heb) PC <= pc_sh;
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else if (ID[15:8]==8'heb) PC <= pc_sh;
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| Line 239... |
Line 243... |
16'hd3xx: nstate = `shift;
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16'hd3xx: nstate = `shift;
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16'hf7e1: nstate = `mul;
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16'hf7e1: nstate = `mul;
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16'hf7f9: nstate = `sdv1;
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16'hf7f9: nstate = `sdv1;
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16'hf7f1: nstate = `div1;
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16'hf7f1: nstate = `div1;
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16'hafc1: nstate = `sml1;
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16'hafc1: nstate = `sml1;
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16'hffd3: nstate = `calla;
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default : nstate = `fetch;
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default : nstate = `fetch;
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endcase
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endcase
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if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
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if (ID == 16'h9066) nprefx = 1'b1; else nprefx = 1'b0;
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if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
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if (ID[15:8] == 8'h39 ) cmpr = 1'b1; else cmpr = 1'b0;
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end
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end
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| Line 273... |
Line 278... |
else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
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else if (state==`jbe) nstate = `jbe2; else if (state==`jbe2) nstate = `fetch;
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else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
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else if (state==`jb ) nstate = `jb2 ; else if (state==`jb2 ) nstate = `fetch;
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else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
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else if (state==`imm) nstate = `imm2; else if (state==`imm2) nstate = `fetch;
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else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
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else if (state==`lea) nstate = `lea2; else if (state==`lea2) nstate = `fetch;
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else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`calla) nstate = `calla2;else if (state==`calla2)nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
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else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
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else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
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else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
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else nstate = `fetch;
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else nstate = `fetch;
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end
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end
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end
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end
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assign ssregsrc = regsrc;
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign ssregdest= regdest;
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assign IA = PC ;
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assign IA = PC ;
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assign A = (state == `call2) ? ESP : EBX ;
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assign A =((state == `call2)|(state == `calla2)) ? ESP : EBX ;
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assign Q = (state == `call2) ? incPC : regsrc ;
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assign Q =((state == `call2)|(state == `calla2)) ? incPC : regsrc ;
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assign WEN = (CE == 1'b0) ? 1'b1 :
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assign WEN = (CE == 1'b0) ? 1'b1 :
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({ID[15:9],ID[7]}==8'h88)? 1'b0 :
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({ID[15:9],ID[7]}==8'h88)? 1'b0 :
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(state == `call2) ? 1'b0 : 1'b1 ;
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(state == `call2) ? 1'b0 :
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(state == `calla2)? 1'b0 : 1'b1 ;
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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{ 24'b0 , regsrc[7:0] } ;
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{ 24'b0 , regsrc[7:0] } ;
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign nlF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign naF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign nbF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign naF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign incPC = PC + 3'b010;
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assign incPC = PC + 3'b010;
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assign pc_jge = (eqF|gF) ? pc_jp : incPC;
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assign pc_jge = (eqF|gF) ? pc_jp : incPC;
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assign pc_jle = (eqF|lF) ? pc_jp : incPC;
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assign pc_jle = (eqF|lF) ? pc_jp : incPC;
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assign pc_jg = (gF ) ? pc_jp : incPC;
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assign pc_jg = (gF ) ? pc_jp : incPC;
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assign pc_jl = (lF ) ? pc_jp : incPC;
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assign pc_jl = (lF ) ? pc_jp : incPC;
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