| Line 63... |
Line 63... |
`define sdv4 6'b101011
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`define sdv4 6'b101011
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`define div1 6'b101100
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`define div1 6'b101100
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`define leas 6'b101101
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`define leas 6'b101101
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`define calla 6'b101110
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`define calla 6'b101110
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`define calla2 6'b101111
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`define calla2 6'b101111
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`define shft3 6'b110000
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`define init 6'b000000
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`define init 6'b000000
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always @(posedge CLK)
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always @(posedge CLK)
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if ((CE ==1'b1) || (RSTN ==1'b0))
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if ((CE ==1'b1) || (RSTN ==1'b0))
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begin
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begin
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| Line 120... |
Line 121... |
endcase
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endcase
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case(state) // EDX control
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case(state) // EDX control
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`init : EDX <= 32'b0;
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`init : EDX <= 32'b0;
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`sdv1 : EDX <= smlEAX;
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`sdv1 : EDX <= smlEAX;
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`div1 : EDX <= EAX;
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`div1 : EDX <= EAX;
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`sdv3 : if (nlF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv3 : if (nbF==1'b0) EDX <= EDX - ECX; else EDX <= EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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`sdv4 : if (EBX[31] == 1'b1) EDX <= ((~EDX) + 1); else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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default : if (dest==3'b010) EDX <= alu_out; else EDX<=EDX;
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endcase
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endcase
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case(state) // ESP control
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case(state) // ESP control
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`init : ESP <= 32'h01ff00;
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`init : ESP <= 32'h01f1fc;
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`call,`calla: ESP <= ESP - 4'b0100;
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`call,`calla: ESP <= ESP - 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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`ret2 : ESP <= ESP + 4'b0100;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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default: if (dest==3'b100) ESP <= alu_out; else ESP<=ESP;
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endcase
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endcase
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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if (dest==3'b101) EBP <= alu_out; else EBP<=EBP; // EBP control
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| Line 282... |
Line 283... |
else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`call) nstate = `call2; else if (state==`call2) nstate = `fetch;
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else if (state==`calla) nstate = `calla2;else if (state==`calla2)nstate = `fetch;
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else if (state==`calla) nstate = `calla2;else if (state==`calla2)nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if (state==`ret) nstate = `ret2; else if (state==`ret2) nstate = `fetch;
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else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
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else if((state==`shift)&&!(EBX_shtr==5'b0)) nstate=`shift;
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else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
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else if((state==`shift)&& (EBX_shtr==5'b0)) nstate=`shft2;
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else if (state==`shft2) nstate = `shft3;
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else nstate = `fetch;
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else nstate = `fetch;
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end
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end
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end
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end
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assign ssregsrc = regsrc;
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assign ssregsrc = regsrc;
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assign ssregdest= regdest;
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assign ssregdest= regdest;
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| Line 298... |
Line 300... |
(state == `calla2)? 1'b0 : 1'b1 ;
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(state == `calla2)? 1'b0 : 1'b1 ;
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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assign Sregsrc = ID[8] ? { {16{regsrc[15]}} , regsrc[15:0] } :
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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{ {24{regsrc[7] }} , regsrc[7:0] } ;
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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assign Zregsrc = ID[8] ? { 16'b0 , regsrc[15:0] } :
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{ 24'b0 , regsrc[7:0] } ;
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{ 24'b0 , regsrc[7:0] } ;
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assign BEN = (state == `call2 ) ? 1'b1 : { prefx , ID[8] } ;
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assign BEN =((state == `call2)|(state == `calla2)) ? 1'b1 : { prefx , ID[8] } ;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign neqF = (regsrc == regdest) ? 1'b1 : 1'b0;
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assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign nbF = (regsrc > regdest) ? 1'b1 : 1'b0;
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assign naF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign naF = ~(nlF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign nlF = (ssregsrc > ssregdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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assign ngF = ~(nbF | neqF );// (regsrc < regdest) ? 1'b1 : 1'b0;
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| Line 326... |
Line 328... |
assign sub_out= regdest - regsrc - nncry;
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assign sub_out= regdest - regsrc - nncry;
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assign nncry = (ID[12] ? cry : 1'b0);
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assign nncry = (ID[12] ? cry : 1'b0);
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assign EBX_shtr = EBX[4:0] - 1'b1;
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assign EBX_shtr = EBX[4:0] - 1'b1;
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assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
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assign smlEAX = EAX[31] ? ((~EAX) + 1) : EAX;
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assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
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assign smlECX = ECX[31] ? ((~ECX) + 1) : ECX;
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assign divF1 = ({ECX[30:0],1'b0} > EDX) ? 1'b1 : 1'b0;
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assign divF1 = ({ECX[31:0],1'b0} > {1'b0,EDX}) ? 1'b1 : 1'b0;
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assign divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
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assign divF2 = (EBX_shtr == 5'b00000) ? 1'b1 : 1'b0;
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endmodule
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endmodule
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