| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: sxp.v,v 1.3 2001-11-06 20:15:28 samg Exp $
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// $Id: sxp.v,v 1.4 2001-11-09 00:45:59 samg Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/11/06 20:15:28 samg
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// Used common header
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//
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//
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//
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|
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// Remove comments to force a syncronous FF bassed reg file.
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// Remove comments to force a syncronous FF bassed reg file.
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// `define SYNC_REG
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// `define SYNC_REG
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| Line 356... |
Line 359... |
dest_en_1 = 1'b 0;
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dest_en_1 = 1'b 0;
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end
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end
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end
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end
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`ifdef SYNC_REG
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`ifdef SYNC_REG
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sync_regf #(4,16) i_regf (
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sync_regf #(4,32) i_regf (
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.clk(clk), // system clock
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.clk(clk), // system clock
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.reset_b(reset_b), // power on reset
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.reset_b(reset_b), // power on reset
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.halt(halt), // system wide halt
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.halt(halt), // system wide halt
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.addra(addra_1), // Port A read address
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.addra(addra_1), // Port A read address
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.a_en(a_en), // Port A read enable
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.a_en(a_en), // Port A read enable
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| Line 371... |
Line 374... |
.wec(wec), // Port C write enable
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.wec(wec), // Port C write enable
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.qra(qra), // Port A registered output data
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.qra(qra), // Port A registered output data
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.qrb(qrb)); // Port B registered output data
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.qrb(qrb)); // Port B registered output data
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`else
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`else
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mem_regf #(4,16) i_regf (
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mem_regf #(4,32) i_regf (
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.clk(clk), // system clock
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.clk(clk), // system clock
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.reset_b(reset_b), // power on reset
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.reset_b(reset_b), // power on reset
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.halt(halt), // system wide halt
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.halt(halt), // system wide halt
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.addra(addra_1), // Port A read address
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.addra(addra_1), // Port A read address
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.a_en(a_en), // Port A read enable
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.a_en(a_en), // Port A read enable
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| Line 387... |
Line 390... |
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.qra(qra), // Port A registered output data
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.qra(qra), // Port A registered output data
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.qrb(qrb)); // Port B registered output data
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.qrb(qrb)); // Port B registered output data
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`endif
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`endif
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regf_status #(4,16) i_regf_status(
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regf_status #(4) i_regf_status(
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.clk(clk), // system clock
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.clk(clk), // system clock
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.reset_b(reset_b), // power on reset
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.reset_b(reset_b), // power on reset
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.stall(stall_1_2), // stall in pipeline 1 and 2
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.stall(stall_1_2), // stall in pipeline 1 and 2
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.halt(halt), // system wide stall signal
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.halt(halt), // system wide stall signal
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.dest_en(dest_en_1), // instr has dest register (en scoreboarding)
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.dest_en(dest_en_1), // instr has dest register (en scoreboarding)
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