| Line 39... |
Line 39... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: sxp.v,v 1.6 2001-12-05 18:12:08 samg Exp $
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// $Id: sxp.v,v 1.7 2001-12-06 16:12:06 samg Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/12/05 18:12:08 samg
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// Rewrote verilog for write enable signals for different destinations in the last stage.
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// The code is much easier to read and more liner to follow.
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//
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// Revision 1.5 2001/12/05 05:58:10 samg
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// Revision 1.5 2001/12/05 05:58:10 samg
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// fixed sensitivity list error in last pipeline stage
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// fixed sensitivity list error in last pipeline stage
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//
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//
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// Revision 1.4 2001/11/09 00:45:59 samg
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// Revision 1.4 2001/11/09 00:45:59 samg
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// integrated common rams into processor
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// integrated common rams into processor
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| Line 693... |
Line 697... |
begin
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begin
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wec = jal_4;
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wec = jal_4;
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set_pc = 1'b 1;
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set_pc = 1'b 1;
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end
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end
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else // Cond jump not taken (nothing done)
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else // Cond jump not taken (nothing done)
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begin
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{wec, set_pc} = 2'b 00;
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wec = 1'b 0;
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set_pc = 1'b 0;
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end
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else // Typical JAL type instruction
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else // Typical JAL type instruction
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begin
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begin
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wec = jal_4;
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wec = jal_4;
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set_pc = 1'b 1;
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set_pc = 1'b 1;
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end
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end
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| Line 711... |
Line 712... |
endcase
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endcase
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else
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else
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{wec, set_pc, spw_we, ext_we} = 4'b 0000;
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{wec, set_pc, spw_we, ext_we} = 4'b 0000;
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end
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end
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assign regc_data = (wec && set_pc) ? pcn_4 : wb_data; // data to write to reg port C
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assign regc_data = (wec && set_pc) ? pcn_4 : wb_data; // data to write to reg port C (JAL or Data)
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assign addrc_wb = dest_addr_4; // reg file write back address
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assign addrc_wb = dest_addr_4; // reg file write back address
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assign nop_detect = inst_vld_4 & ~(wec | set_pc | spw_we | ext_we); // 1 when no operation is being done
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assign nop_detect = inst_vld_4 & ~(wec | set_pc | spw_we | ext_we); // 1 when no operation is being done
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assign extw_data = wb_data; // extension data for writing
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assign extw_data = wb_data; // extension data for writing
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