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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Id: sxp.v,v 1.8 2001-12-12 02:07:25 samg Exp $
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// $Id: sxp.v,v 1.9 2001-12-14 16:53:12 samg Exp $
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2001/12/12 02:07:25 samg
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// fixed case statement, sensitivity list
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//
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// Revision 1.7 2001/12/06 16:12:06 samg
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// Revision 1.7 2001/12/06 16:12:06 samg
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// minor expression rewrite in 4th stage
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// minor expression rewrite in 4th stage
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//
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//
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// Revision 1.6 2001/12/05 18:12:08 samg
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// Revision 1.6 2001/12/05 18:12:08 samg
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// Rewrote verilog for write enable signals for different destinations in the last stage.
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// Rewrote verilog for write enable signals for different destinations in the last stage.
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`endif
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`endif
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regf_status #(4) i_regf_status(
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regf_status #(4) i_regf_status(
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.clk(clk), // system clock
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.clk(clk), // system clock
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.reset_b(reset_b), // power on reset
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.reset_b(reset_b), // power on reset
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.stall(stall_1_2), // stall in pipeline 1 and 2
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.halt(halt), // system wide stall signal
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.halt(halt), // system wide stall signal
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.dest_en(dest_en_1), // instr has dest register (en scoreboarding)
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.dest_en(dest_en_1), // instr has dest register (en scoreboarding)
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.dest_addr(dest_addr_1), // destination address from instruction
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.dest_addr(dest_addr_1), // destination address from instruction
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.wec(wec), // port C write back request
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.wec(wec), // port C write back request
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.addrc(addrc_wb), // port C write back address
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.addrc(addrc_wb), // port C write back address
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.a_en(a_en), // Reg A is enabled in instruction
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.a_en(a_en), // Reg A is enabled in instruction
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.b_en(b_en), // Reg B is enabled in instruction
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.b_en(b_en), // Reg B is enabled in instruction
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.flush_pipeline(flush_pipeline),// Reinitialize status after pipeline flush
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.flush_pipeline(flush_pipeline),// Reinitialize status after pipeline flush
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.safe_switch(safe_switch), // safe to context switch or interupt;
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.safe_switch(safe_switch), // safe to context switch or interupt;
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.stall_regf(stall_1_2)); // stall the reg file and modules prior
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.conflict(stall_1_2)); // stall the reg file and modules prior
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`ifdef SYNC_REG
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`ifdef SYNC_REG
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always @(inst_vld_1 or stall_1_2 or dest_cfg_1 or dest_addr_1 or src_cfg_1 or
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always @(inst_vld_1 or stall_1_2 or dest_cfg_1 or dest_addr_1 or src_cfg_1 or
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alu_cfg_1 or wb_cfg_1 or imm_1 or pcn_1 or cond_jump_1 or b_en or
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alu_cfg_1 or wb_cfg_1 or imm_1 or pcn_1 or cond_jump_1 or b_en or
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