| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2005/07/29 09:13:06 jcastillo
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// Correct bit 28 of CASR
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//
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// Revision 1.1 2004/09/23 09:43:06 jcastillo
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// Revision 1.1 2004/09/23 09:43:06 jcastillo
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// Verilog first import
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// Verilog first import
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//
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//
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|
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`timescale 10ns/1ns
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`timescale 10ns/1ns
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| Line 86... |
Line 89... |
|
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if (loadseed_i )
|
if (loadseed_i )
|
|
|
begin
|
begin
|
|
|
CASR_varCASR [36:31]=0;
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CASR_varCASR [36:32]=0;
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CASR_varCASR [31:0]=seed_i ;
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CASR_varCASR [31:0]=seed_i ;
|
CASR_reg = (CASR_varCASR );
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CASR_reg = (CASR_varCASR );
|
|
|
|
|
end
|
end
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| Line 107... |
Line 110... |
CASR_outCASR [33]=CASR_varCASR [32]^CASR_varCASR [34];
|
CASR_outCASR [33]=CASR_varCASR [32]^CASR_varCASR [34];
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CASR_outCASR [32]=CASR_varCASR [31]^CASR_varCASR [33];
|
CASR_outCASR [32]=CASR_varCASR [31]^CASR_varCASR [33];
|
CASR_outCASR [31]=CASR_varCASR [30]^CASR_varCASR [32];
|
CASR_outCASR [31]=CASR_varCASR [30]^CASR_varCASR [32];
|
CASR_outCASR [30]=CASR_varCASR [29]^CASR_varCASR [31];
|
CASR_outCASR [30]=CASR_varCASR [29]^CASR_varCASR [31];
|
CASR_outCASR [29]=CASR_varCASR [28]^CASR_varCASR [30];
|
CASR_outCASR [29]=CASR_varCASR [28]^CASR_varCASR [30];
|
CASR_outCASR [28]=CASR_varCASR [27]^CASR_varCASR [28]^CASR_varCASR [29];
|
CASR_outCASR [28]=CASR_varCASR [27]^CASR_varCASR [29];
|
CASR_outCASR [27]=CASR_varCASR [26]^CASR_varCASR [28];
|
CASR_outCASR [27]=CASR_varCASR [26]^CASR_varCASR [27]^CASR_varCASR [28];
|
CASR_outCASR [26]=CASR_varCASR [25]^CASR_varCASR [27];
|
CASR_outCASR [26]=CASR_varCASR [25]^CASR_varCASR [27];
|
CASR_outCASR [25]=CASR_varCASR [24]^CASR_varCASR [26];
|
CASR_outCASR [25]=CASR_varCASR [24]^CASR_varCASR [26];
|
CASR_outCASR [24]=CASR_varCASR [23]^CASR_varCASR [25];
|
CASR_outCASR [24]=CASR_varCASR [23]^CASR_varCASR [25];
|
CASR_outCASR [23]=CASR_varCASR [22]^CASR_varCASR [24];
|
CASR_outCASR [23]=CASR_varCASR [22]^CASR_varCASR [24];
|
CASR_outCASR [22]=CASR_varCASR [21]^CASR_varCASR [23];
|
CASR_outCASR [22]=CASR_varCASR [21]^CASR_varCASR [23];
|
| Line 170... |
Line 173... |
|
|
if (loadseed_i )
|
if (loadseed_i )
|
|
|
begin
|
begin
|
|
|
LFSR_varLFSR [42:31]=0;
|
LFSR_varLFSR [42:32]=0;
|
LFSR_varLFSR [31:0]=seed_i ;
|
LFSR_varLFSR [31:0]=seed_i ;
|
LFSR_reg = (LFSR_varLFSR );
|
LFSR_reg = (LFSR_varLFSR );
|
|
|
|
|
end
|
end
|
