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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_wrapper.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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import uart_top_package:: * ;
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module uart_wrapper (interface wb_ext_bus, interface uart_bus) ;
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logic [31:0] dat_o ;
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logic ack_o ;
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logic intr_o ;
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logic stx_o ;
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logic rts_o ;
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logic dtr_o ;
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wire clk_i = wb_ext_bus.clk_i ;
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wire nrst_i = wb_ext_bus.nrst_i ;
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wire [15:0] adr_i = wb_ext_bus.adr_i ;
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wire [31:0] dat_i = wb_ext_bus.dat_i ;
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wire we_i = wb_ext_bus.we_i ;
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wire [3:0] sel_i = wb_ext_bus.sel_i ;
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wire stb_i = wb_ext_bus.stb_i ;
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wire cyc_i = wb_ext_bus.cyc_i ;
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assign wb_ext_bus.dat_o = dat_o ;
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assign wb_ext_bus.ack_o = ack_o ;
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assign wb_ext_bus.intr_o = intr_o ;
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assign uart_bus.stx_o = stx_o ;
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assign uart_bus.rts_o = rts_o ;
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assign uart_bus.dtr_o = dtr_o ;
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wire srx_i = uart_bus.srx_i ;
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wire cts_i = uart_bus.cts_i ;
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wire dsr_i = uart_bus.dsr_i ;
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wire ri_i = uart_bus.ri_i ;
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wire dcd_i = uart_bus.dcd_i ;
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uart_top ut(.*) ;
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endmodule
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