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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_16550_rll.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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module uart_16550_rll(interface wb_bus, uart_bus uart_bus) ;
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import uart_package:: * ;
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wire clk_i = wb_bus.clk_i ;
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wire nrst_i = wb_bus.nrst_i ;
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wire overrun ;
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wire rec_buf_empty ;
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wire trans_buf_empty ;
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wire rec_clk_en ;
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wire rec_sample_pulse ;
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wire leading_edge ;
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wire trans_clk_en ;
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wire txd_out ;
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wire rxd_clean ;
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wire rxd_clean_out ;
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wire timeout_signal ;
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fifo_bus
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fifo_pop_trans(.clk_i(clk_i)),
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fifo_push_rec(.clk_i(clk_i)) ;
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// uart_bus uart_bus() ;
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u_reg_t u_reg ;
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codec_state_t rec_next_state ;
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u_codec_t trans_codec ;
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// -- loopback mode --
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assign uart_bus.stx_o = u_reg.modem_control_reg.loopback == 1'b1 ? 1'b1 : txd_out ;
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assign rxd_clean = u_reg.modem_control_reg.loopback == 1'b1 ? txd_out : rxd_clean_out ;
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uart_register u_register(.clk_i(clk_i),
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.nrst_i(nrst_i),
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.wb_bus(wb_bus),
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.uart_bus(uart_bus),
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.u_reg(u_reg),
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.fifo_pop_trans(fifo_pop_trans),
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.fifo_push_rec(fifo_push_rec),
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.timeout_signal(timeout_signal),
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.overrun(overrun),
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.rec_buf_empty(rec_buf_empty),
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.trans_buf_empty(trans_buf_empty)) ;
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uart_transmitter u_trans(.clk_i(clk_i),
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.nrst_i(nrst_i),
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.trans_clk_en(trans_clk_en),
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.txd_out(txd_out),
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.fifo_pop(fifo_pop_trans.pop_master_mp),
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.u_reg(u_reg),
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.trans_codec(trans_codec),
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.trans_buf_empty(trans_buf_empty)) ;
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uart_receiver u_rec(.clk_i(clk_i),
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.nrst_i(nrst_i),
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.rec_clk_en(rec_clk_en),
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.rec_sample_pulse(rec_sample_pulse),
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.rxd_clean(rxd_clean),
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.leading_edge(leading_edge),
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.timeout_signal(timeout_signal),
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.fifo_push(fifo_push_rec.push_master_mp),
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.u_reg(u_reg),
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.next_state(rec_next_state),
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.overrun(overrun),
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.rec_buf_empty(rec_buf_empty)) ;
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uart_baud u_baud(.clk_i(clk_i),
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.nrst_i(nrst_i),
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.u_reg(u_reg),
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.rec_next_state(rec_next_state),
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.trans_codec(trans_codec),
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.rxd_clean(rxd_clean),
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.rec_clk_en(rec_clk_en),
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.rec_sample_pulse(rec_sample_pulse),
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.leading_edge(leading_edge),
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.timeout_signal(timeout_signal),
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.trans_clk_en(trans_clk_en)) ;
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uart_noize_shaver u_shaver(.clk_i(clk_i),
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.nrst_i(nrst_i),
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.rxd_i(uart_bus.srx_i),
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.rxd_clean(rxd_clean_out)) ;
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endmodule
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/// END OF FILE ///
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