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/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_test.sv 112 2010-03-30 04:37:33Z hiroshi $ *
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***************************************************************************** */
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#(STEP*100) ;
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$display("char7 pari non, buad rate setup 19200bps") ;
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$fdisplay(file_a, "char7 pari non, buad rate setup 19200bps") ;
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UART_R = 0 ; // all cleaer register
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$display("fifo trigger level 14byte") ;
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$fdisplay(file_a, "fifo trigger level 14byte") ;
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UART_R.fifo_control_reg.define_fifo_trigger_level = BYTE_14 ;
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wb_DUT.write( UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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wb_BENCH.write(UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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UART_R.line_control_reg.divisor_access = 1'b1 ;
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UART_R.baud_reg = 8'd64 ; // 19200bps
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wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_BENCH.write(UART_R.baud_reg, UART_BAUD) ;
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wb_DUT.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.write(UART_R.baud_reg, UART_BAUD) ;
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// --
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UART_R.line_control_reg.divisor_access = 1'b0 ;
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UART_R.line_control_reg.char_length = CHAR_7_BIT ;
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UART_R.line_control_reg.parity_enable = 1'b0 ;
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UART_R.line_control_reg.even_parity = 1'b1 ;
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wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.write( UART_R.line_control_reg, UART_LINE_CONTROL) ;
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UART_R.interrupt_enable_reg.trans_holding_reg_empty = 1'b1 ;
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wb_DUT.write(UART_R.interrupt_enable_reg, UART_INTERRUPT_ENABLE) ;
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wb_DUT.nop() ;
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wdat = 1 ;
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for(i=0;i<8;i+=1) begin
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wb_DUT.write(wdat<
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end
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@(posedge intr_o) ;
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#(STEP*13000) ;
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for(i=0;i<8;i+=1) begin
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wb_BENCH.read(rdat, UART_RXD) ;
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$display("read data = %x", rdat) ;
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$fdisplay(file_a, "read data = %x", rdat) ;
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end
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$display("fifo clear") ;
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$fdisplay(file_a, "fifo clear") ;
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UART_R.fifo_control_reg.transmitter_fifo_reset = 1'b1 ;
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UART_R.fifo_control_reg.receiver_fifo_reset = 1'b1 ;
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wb_DUT.write( UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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wb_BENCH.write(UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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$display("char7 pari even") ;
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$fdisplay(file_a, "char7 pari even") ;
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UART_R.line_control_reg.parity_enable = 1'b1 ;
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UART_R.line_control_reg.even_parity = 1'b1 ;
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wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.write( UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.nop() ;
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wdat = 1 ;
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for(i=0;i<8;i+=1) begin
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wb_DUT.write(wdat<
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end
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@(posedge intr_o) ;
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#(STEP*13000) ;
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$display("char7 pari odd") ;
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$fdisplay(file_a, "char7 pari odd") ;
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UART_R.line_control_reg.even_parity = 1'b0 ;
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wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.write( UART_R.line_control_reg, UART_LINE_CONTROL) ;
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wb_DUT.nop() ;
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wdat = 1 ;
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for(i=0;i<8;i+=1) begin
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wb_DUT.write(wdat<
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end
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@(posedge intr_o) ;
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#(STEP*13000) ;
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for(i=0;i<16;i+=1) begin
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wb_BENCH.read(rdat, UART_RXD) ;
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$display("read data = %x", rdat) ;
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$fdisplay(file_a, "read data = %x", rdat) ;
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end
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#(STEP*300) ;
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$display("fifo clear") ;
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$fdisplay(file_a, "fifo clear") ;
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UART_R.fifo_control_reg.transmitter_fifo_reset = 1'b1 ;
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UART_R.fifo_control_reg.receiver_fifo_reset = 1'b1 ;
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wb_DUT.write( UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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wb_BENCH.write(UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
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UART_R.interrupt_enable_reg.trans_holding_reg_empty = 1'b1 ;
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wb_BENCH.write(UART_R.interrupt_enable_reg, UART_INTERRUPT_ENABLE) ;
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UART_R.interrupt_enable_reg.trans_holding_reg_empty = 1'b0 ;
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UART_R.interrupt_enable_reg.rec_data_available = 1'b1 ;
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wb_DUT.write(UART_R.interrupt_enable_reg, UART_INTERRUPT_ENABLE) ;
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wb_DUT.read(rdat, UART_INTERRUPT_IDENT) ;
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wb_DUT.nop() ;
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for(i=0;i<4;i+=1) begin
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wb_BENCH.write(wdat<
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end
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@(posedge intr_o) ;
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$display("timeout intr -> accept") ;
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$fdisplay(file_a, "timeout intr -> accept") ;
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wb_DUT.read(rdat, UART_LINE_STATUS) ;
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$display("line_status = %b", rdat) ;
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$fdisplay(file_a, "line_status = %b", rdat) ;
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wb_DUT.read(rdat, UART_INTERRUPT_IDENT) ;
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$display("interrupt_ident = %b", rdat) ;
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$fdisplay(file_a, "interrupt_ident = %b", rdat) ;
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wb_DUT.read(rdat, UART_RXD) ;
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wb_DUT.read(rdat, UART_INTERRUPT_IDENT) ;
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$display("interrupt_ident = %b", rdat) ;
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$fdisplay(file_a, "interrupt_ident = %b", rdat) ;
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#(STEP*500) ;
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