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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Testbench for interrupt evaluation.
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-- Testbench for interrupt evaluation.
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--
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--
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-- $Id: tb_int.vhd,v 1.4 2006-05-28 23:09:20 arniml Exp $
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-- $Id: tb_int.vhd,v 1.5 2006-06-05 18:50:45 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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architecture behav of tb_int is
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architecture behav of tb_int is
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-- 210.4 kHz clock
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-- 210.4 kHz clock
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constant period_c : time := 4.75 us;
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constant period_c : time := 4.75 us;
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signal ck_s : std_logic;
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signal ck_s : std_logic;
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signal en_ck_s : std_logic;
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signal reset_n_s : std_logic;
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signal reset_n_s : std_logic;
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signal io_l_s : std_logic_vector(7 downto 0);
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signal io_l_s : std_logic_vector(7 downto 0);
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signal io_d_s : std_logic_vector(3 downto 0);
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signal io_d_s : std_logic_vector(3 downto 0);
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| Line 194... |
Line 193... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2006/05/28 23:09:20 arniml
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-- lower nibble is OD to prevent contention with testbench
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--
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-- Revision 1.3 2006/05/28 15:36:59 arniml
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-- Revision 1.3 2006/05/28 15:36:59 arniml
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-- don't generate interrupt when in interrupt routine around 0x100
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-- don't generate interrupt when in interrupt routine around 0x100
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--
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--
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-- Revision 1.2 2006/05/28 02:53:47 arniml
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-- Revision 1.2 2006/05/28 02:53:47 arniml
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-- provide SA at L port
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-- provide SA at L port
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