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Rev 91 |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Testbench for interrupt evaluation.
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-- Testbench for interrupt evaluation.
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--
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--
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-- $Id: tb_int.vhd,v 1.2 2006-05-28 02:53:47 arniml Exp $
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-- $Id: tb_int.vhd,v 1.3 2006-05-28 15:36:59 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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case to_integer(tb_pc_s) is
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case to_integer(tb_pc_s) is
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when 16#030# =>
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when 16#030# =>
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int_v := '0';
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int_v := '0';
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when 16#0b0# =>
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when 16#0b0# =>
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int_v := '0';
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int_v := '0';
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when 16#130# =>
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int_v := '0';
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when 16#1b0# =>
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when 16#1b0# =>
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int_v := '0';
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int_v := '0';
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when 16#230# =>
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when 16#230# =>
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int_v := '0';
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int_v := '0';
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when 16#2b0# =>
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when 16#2b0# =>
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Line 190... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2006/05/28 02:53:47 arniml
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-- provide SA at L port
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--
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-- Revision 1.1 2006/05/27 19:08:21 arniml
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-- Revision 1.1 2006/05/27 19:08:21 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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