| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- Testbench for the T411 system toplevel.
|
-- Testbench for the T411 system toplevel.
|
--
|
--
|
-- $Id: tb_t411.vhd,v 1.5 2006-05-27 19:10:12 arniml Exp $
|
-- $Id: tb_t411.vhd,v 1.6 2006-06-05 18:50:45 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 58... |
Line 58... |
architecture behav of tb_t411 is
|
architecture behav of tb_t411 is
|
|
|
-- 210.4 kHz clock
|
-- 210.4 kHz clock
|
constant period_c : time := 4.75 us;
|
constant period_c : time := 4.75 us;
|
signal ck_s : std_logic;
|
signal ck_s : std_logic;
|
signal en_ck_s : std_logic;
|
|
|
|
signal reset_n_s : std_logic;
|
signal reset_n_s : std_logic;
|
|
|
signal io_l_s : std_logic_vector(7 downto 0);
|
signal io_l_s : std_logic_vector(7 downto 0);
|
signal io_d_s : std_logic_vector(1 downto 0);
|
signal io_d_s : std_logic_vector(1 downto 0);
|
| Line 129... |
Line 128... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.5 2006/05/27 19:10:12 arniml
|
|
-- explicitly select clock divider 8
|
|
--
|
-- Revision 1.4 2006/05/23 01:18:26 arniml
|
-- Revision 1.4 2006/05/23 01:18:26 arniml
|
-- consider IN port
|
-- consider IN port
|
--
|
--
|
-- Revision 1.3 2006/05/15 21:56:02 arniml
|
-- Revision 1.3 2006/05/15 21:56:02 arniml
|
-- moved elements to separate design unit tb_elems
|
-- moved elements to separate design unit tb_elems
|
