| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Testbench for the T411 system toplevel.
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-- Testbench for the T411 system toplevel.
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--
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--
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-- $Id: tb_t411.vhd,v 1.2 2006-05-06 13:34:25 arniml Exp $
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-- $Id: tb_t411.vhd,v 1.3 2006-05-15 21:56:02 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 48... |
Line 48... |
end tb_t411;
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end tb_t411;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.t400_system_comp_pack.t411;
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use work.t400_system_comp_pack.t411;
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use work.tb_pack.tb_elems;
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|
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architecture behav of tb_t411 is
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architecture behav of tb_t411 is
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|
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-- 210.4 kHz clock
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-- 210.4 kHz clock
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-- -> 52.6 kHz internal clock
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-- -> 52.6 kHz internal clock
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| Line 74... |
Line 74... |
|
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signal vdd_s : std_logic;
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signal vdd_s : std_logic;
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begin
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begin
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en_ck_s <= 'H';
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vdd_s <= '1';
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vdd_s <= '1';
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reset_n_s <= '1';
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reset_n_s <= '1';
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 101... |
Line 100... |
io_d_s <= (others => 'H');
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io_d_s <= (others => 'H');
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io_g_s <= (others => 'H');
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io_g_s <= (others => 'H');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Pass/fail catcher
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-- Testbench elements
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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pass_fail: process (io_l_s)
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tb_elems_b : tb_elems
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type pass_fail_t is (IDLE,
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generic map (
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GOT_0, GOT_A, GOT_5);
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period_g => period_c,
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variable state_v : pass_fail_t := IDLE;
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d_width_g => 2,
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variable sig_v : std_logic_vector(3 downto 0);
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g_width_g => 3
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begin
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)
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sig_v := to_X01(io_l_s(7 downto 4));
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port map (
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io_l_i => io_l_s,
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case state_v is
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io_d_i => io_d_s,
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when IDLE =>
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io_g_i => io_g_s,
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en_ck_s <= 'Z';
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so_i => so_s,
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if sig_v = "0000" then
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si_o => si_s,
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state_v := GOT_0;
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sk_i => sk_s,
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end if;
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ck_o => ck_s
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when GOT_0 =>
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);
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if sig_v = "1010" then
|
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state_v := GOT_A;
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elsif sig_v /= "0000" then
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state_v := IDLE;
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end if;
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when GOT_A =>
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if sig_v = "0101" then
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state_v := GOT_5;
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elsif sig_v /= "1010" then
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state_v := IDLE;
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end if;
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when GOT_5 =>
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if sig_v = "0000" then
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en_ck_s <= '0';
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assert false
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report "Simulation finished with PASS."
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severity note;
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elsif sig_v = "1111" then
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en_ck_s <= '0';
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assert false
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report "Simulation finished with FAIL."
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severity note;
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elsif sig_v /= "0101" then
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state_v := IDLE;
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end if;
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end case;
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end process pass_fail;
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-----------------------------------------------------------------------------
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-- D monitor
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-----------------------------------------------------------------------------
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d_moni: process (io_d_s)
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type d_moni_t is (IDLE,
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STEP_1, STEP_2);
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variable state_v : d_moni_t := IDLE;
|
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variable sig_v : unsigned(3 downto 0);
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begin
|
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sig_v := (others => '0');
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sig_v(io_d_s'range) := unsigned(to_X01(io_d_s));
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|
|
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case state_v is
|
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when IDLE =>
|
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en_ck_s <= 'Z';
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if sig_v = 1 then
|
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state_v := STEP_1;
|
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end if;
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when STEP_1 =>
|
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if sig_v = 2 then
|
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state_v := STEP_2;
|
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else
|
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state_v := IDLE;
|
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end if;
|
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when STEP_2 =>
|
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if sig_v /= 0 then
|
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state_v := IDLE;
|
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else
|
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en_ck_s <= '0';
|
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assert false
|
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report "Simulation finished with PASS (D-Port)."
|
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severity note;
|
|
end if;
|
|
|
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when others =>
|
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null;
|
|
end case;
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|
|
|
end process d_moni;
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|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- G monitor
|
|
-----------------------------------------------------------------------------
|
|
g_moni: process (io_g_s)
|
|
type d_moni_t is (IDLE,
|
|
STEP_1, STEP_2, STEP_3);
|
|
variable state_v : d_moni_t := IDLE;
|
|
variable sig_v : unsigned(3 downto 0);
|
|
begin
|
|
sig_v := (others => '0');
|
|
sig_v(io_g_s'range) := unsigned(to_X01(io_g_s));
|
|
|
|
case state_v is
|
|
when IDLE =>
|
|
en_ck_s <= 'Z';
|
|
if sig_v = 1 then
|
|
state_v := STEP_1;
|
|
end if;
|
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when STEP_1 =>
|
|
if sig_v = 2 then
|
|
state_v := STEP_2;
|
|
else
|
|
state_v := IDLE;
|
|
end if;
|
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when STEP_2 =>
|
|
if sig_v = 4 then
|
|
state_v := STEP_3;
|
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else
|
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state_v := IDLE;
|
|
end if;
|
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when STEP_3 =>
|
|
if sig_v /= 0 then
|
|
state_v := IDLE;
|
|
else
|
|
en_ck_s <= '0';
|
|
assert false
|
|
report "Simulation finished with PASS (G-Port)."
|
|
severity note;
|
|
end if;
|
|
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
end process g_moni;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- SIO peer
|
|
-----------------------------------------------------------------------------
|
|
sio_peer: process
|
|
begin
|
|
si_s <= '0';
|
|
|
|
wait until io_l_s(4) = '0';
|
|
|
|
while io_l_s(4) = '0' loop
|
|
wait for 10 us;
|
|
si_s <= so_s xor sk_s;
|
|
|
|
wait until io_l_s'event or so_s'event or sk_s'event;
|
|
end loop;
|
|
|
|
-- now feed SO back to SI upon SK edge
|
|
loop
|
|
wait until sk_s'event and sk_s = '1';
|
|
wait for 10 us;
|
|
si_s <= so_s;
|
|
end loop;
|
|
|
|
wait;
|
|
end process sio_peer;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Clock generator
|
|
-----------------------------------------------------------------------------
|
|
clk: process
|
|
begin
|
|
ck_s <= '0';
|
|
wait for period_c / 2;
|
|
ck_s <= '1';
|
|
wait for period_c / 2;
|
|
|
|
if to_X01(en_ck_s) /= '1' then
|
|
wait;
|
|
end if;
|
|
end process clk;
|
|
|
|
end behav;
|
end behav;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2006/05/06 13:34:25 arniml
|
|
-- remove delta cycle filter on sk_s
|
|
--
|
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
|
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
|
-- import from local CVS repository, LOC_CVS_0_1
|
-- import from local CVS repository, LOC_CVS_0_1
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
