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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T400 Microcontroller Core
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-- T400 Microcontroller Core
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--
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--
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-- $Id: t400_core.vhd,v 1.4 2006-05-22 00:03:29 arniml Exp $
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-- $Id: t400_core.vhd,v 1.5 2006-05-23 01:13:56 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 162... |
skip_lbi_s : boolean;
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skip_lbi_s : boolean;
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signal tim_c_s : boolean;
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signal tim_c_s : boolean;
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signal in_s : dw_t;
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signal in_s : dw_t;
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signal io_g_s : std_logic_vector(io_g_i'range);
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signal vdd_s : std_logic;
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signal vdd_s : std_logic;
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signal gnd4_s : dw_t;
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signal gnd4_s : dw_t;
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begin
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begin
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Line 176... |
gnd4_s <= (others => '0');
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gnd4_s <= (others => '0');
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ck_en_s <= ck_en_i = '1';
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ck_en_s <= ck_en_i = '1';
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por_s <= por_n_i = '0';
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por_s <= por_n_i = '0';
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io_g_s <= to_X01(io_g_i);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Clock generator
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-- Clock generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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clkgen_b : t400_clkgen
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clkgen_b : t400_clkgen
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generic map (
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generic map (
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Line 311... |
c_i => c_s,
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c_i => c_s,
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bd_i => b_s(bd_range_t),
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bd_i => b_s(bd_range_t),
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is_lbi_i => is_lbi_s,
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is_lbi_i => is_lbi_s,
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a_i => a_s,
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a_i => a_s,
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m_i => dm_data_i,
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m_i => dm_data_i,
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g_i => io_g_i,
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g_i => io_g_s,
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tim_c_i => tim_c_s,
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tim_c_i => tim_c_s,
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skip_o => skip_s,
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skip_o => skip_s,
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skip_lbi_o => skip_lbi_s
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skip_lbi_o => skip_lbi_s
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);
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);
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Line 336... |
op_i => alu_op_s,
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op_i => alu_op_s,
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m_i => dm_data_i,
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m_i => dm_data_i,
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dec_data_i => dec_data_s,
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dec_data_i => dec_data_s,
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q_low_i => q_s(3 downto 0),
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q_low_i => q_s(3 downto 0),
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b_i => b_s,
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b_i => b_s,
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g_i => io_g_i,
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g_i => io_g_s,
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in_i => in_s,
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in_i => in_s,
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sio_i => sio_s,
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sio_i => sio_s,
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a_o => a_s,
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a_o => a_s,
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carry_o => carry_s,
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carry_o => carry_s,
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c_o => c_s
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c_o => c_s
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Line 520... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2006/05/22 00:03:29 arniml
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-- io_in added
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--
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-- Revision 1.3 2006/05/21 21:47:40 arniml
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-- Revision 1.3 2006/05/21 21:47:40 arniml
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-- route cko to ALU for INIL instruction
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-- route cko to ALU for INIL instruction
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--
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--
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-- Revision 1.2 2006/05/20 02:48:17 arniml
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-- Revision 1.2 2006/05/20 02:48:17 arniml
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-- timer module included
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-- timer module included
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