| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The decoder unit.
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-- The decoder unit.
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-- Implements the instruction opcodes and controls all units of the T400 core.
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-- Implements the instruction opcodes and controls all units of the T400 core.
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--
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--
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-- $Id: t400_decoder.vhd,v 1.4 2006-05-27 19:14:18 arniml Exp $
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-- $Id: t400_decoder.vhd,v 1.5 2006-05-28 15:32:14 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 208... |
Line 208... |
end if;
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end if;
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end if;
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end if;
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-- instruction byte 1 and mnemonic info -------------------------------
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-- instruction byte 1 and mnemonic info -------------------------------
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if icyc_en_i and last_cycle_s then
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if icyc_en_i and last_cycle_s then
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if not ack_int_s then
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-- update instruction descriptors in normal mode
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ibyte1_q <= pm_data_i;
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ibyte1_q <= pm_data_i;
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mnemonic_q <= mnemonic_s;
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mnemonic_q <= mnemonic_s;
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multi_byte_q <= multi_byte_s;
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multi_byte_q <= multi_byte_s;
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else
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-- force NOP instruction when vectoring to interrupt routine
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ibyte1_q <= "01000100";
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mnemonic_q <= MN_NOP;
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multi_byte_q <= false;
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end if;
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end if;
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end if;
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-- instruction byte 2 -------------------------------------------------
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-- instruction byte 2 -------------------------------------------------
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if icyc_en_i and not last_cycle_s then
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if icyc_en_i and not last_cycle_s then
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ibyte2_q <= pm_data_i;
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ibyte2_q <= pm_data_i;
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| Line 271... |
Line 279... |
en_q, int_i,
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en_q, int_i,
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pm_addr_i, pm_data_i)
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pm_addr_i, pm_data_i)
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variable cyc_v : natural range 0 to 4;
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variable cyc_v : natural range 0 to 4;
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variable t41x_type_v,
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variable t41x_type_v,
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t420_type_v : boolean;
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t420_type_v : boolean;
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variable no_int_v : boolean;
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variable en_int_v : boolean;
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begin
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begin
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-- default assignments
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-- default assignments
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pc_op_o <= PC_NONE;
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pc_op_o <= PC_NONE;
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stack_op_o <= STACK_NONE;
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stack_op_o <= STACK_NONE;
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dmem_op_o <= DMEM_RB; -- default is read via B
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dmem_op_o <= DMEM_RB; -- default is read via B
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| Line 289... |
Line 297... |
sio_op_o <= SIO_NONE;
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sio_op_o <= SIO_NONE;
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dec_data_o <= (others => '0');
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dec_data_o <= (others => '0');
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is_lbi_o <= false;
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is_lbi_o <= false;
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set_en_s <= false;
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set_en_s <= false;
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force_mc_s <= false;
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force_mc_s <= false;
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no_int_v := false;
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en_int_v := true;
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ack_int_s <= false;
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ack_int_s <= false;
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cyc_v := to_integer(cyc_cnt_q);
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cyc_v := to_integer(cyc_cnt_q);
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-- determine type
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-- determine type
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t41x_type_v := opt_type_g = t400_opt_type_410_c;
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t41x_type_v := opt_type_g = t400_opt_type_410_c;
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t420_type_v := opt_type_g = t400_opt_type_420_c;
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t420_type_v := opt_type_g = t400_opt_type_420_c;
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| Line 388... |
Line 396... |
end if;
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end if;
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-- Mnemonic JID -------------------------------------------------------
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-- Mnemonic JID -------------------------------------------------------
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when MN_JID =>
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when MN_JID =>
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force_mc_s <= true;
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force_mc_s <= true;
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no_int_v := true;
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en_int_v := false;
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dec_data_o(byte_t'range) <= pm_data_i;
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dec_data_o(byte_t'range) <= pm_data_i;
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if cyc_v = 1 then
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if cyc_v = 1 then
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if not second_cyc_q then
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if not second_cyc_q then
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-- first cycle: load PC from A and M
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-- first cycle: load PC from A and M
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pc_op_o <= PC_LOAD_A_M;
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pc_op_o <= PC_LOAD_A_M;
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| Line 407... |
Line 415... |
pc_op_o <= PC_NONE;
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pc_op_o <= PC_NONE;
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end if;
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end if;
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-- Mnemonic JMP -------------------------------------------------------
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-- Mnemonic JMP -------------------------------------------------------
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when MN_JMP =>
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when MN_JMP =>
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no_int_v := true;
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en_int_v := false;
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dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
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dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
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if second_cyc_q and cyc_v = 1 then
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if second_cyc_q and cyc_v = 1 then
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pc_op_o <= PC_LOAD;
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pc_op_o <= PC_LOAD;
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end if;
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end if;
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-- Mnemonic JP_JSRP ---------------------------------------------------
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-- Mnemonic JP_JSRP ---------------------------------------------------
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when MN_JP_JSRP =>
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when MN_JP_JSRP =>
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no_int_v := true;
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en_int_v := false;
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-- universal decoder data
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-- universal decoder data
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dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
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dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
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if cyc_v = 1 then
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if cyc_v = 1 then
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if pm_addr_i(9 downto 7) = "001" then
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if pm_addr_i(9 downto 7) = "001" then
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-- JP within pages 2 & 3
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-- JP within pages 2 & 3
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| Line 434... |
Line 442... |
end if;
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end if;
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end if;
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end if;
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-- Mnemonic JSR -------------------------------------------------------
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-- Mnemonic JSR -------------------------------------------------------
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when MN_JSR =>
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when MN_JSR =>
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no_int_v := true;
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en_int_v := false;
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dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
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dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
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if second_cyc_q and cyc_v = 1 then
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if second_cyc_q and cyc_v = 1 then
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pc_op_o <= PC_LOAD;
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pc_op_o <= PC_LOAD;
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stack_op_o <= STACK_PUSH;
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stack_op_o <= STACK_PUSH;
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end if;
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end if;
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-- Mnemonic RET -------------------------------------------------------
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-- Mnemonic RET -------------------------------------------------------
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when MN_RET =>
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when MN_RET =>
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no_int_v := true;
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en_int_v := false;
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if cyc_v = 1 then
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if cyc_v = 1 then
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pc_op_o <= PC_POP;
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pc_op_o <= PC_POP;
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stack_op_o <= STACK_POP;
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stack_op_o <= STACK_POP;
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if t420_type_v then
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if t420_type_v then
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| Line 456... |
Line 464... |
end if;
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end if;
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end if;
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end if;
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-- Mnemonic RETSK -----------------------------------------------------
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-- Mnemonic RETSK -----------------------------------------------------
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when MN_RETSK =>
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when MN_RETSK =>
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no_int_v := true;
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en_int_v := false;
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if cyc_v = 1 then
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if cyc_v = 1 then
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pc_op_o <= PC_POP;
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pc_op_o <= PC_POP;
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stack_op_o <= STACK_POP;
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stack_op_o <= STACK_POP;
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skip_op_o <= SKIP_NOW;
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skip_op_o <= SKIP_NOW;
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end if;
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end if;
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| Line 513... |
Line 521... |
end if;
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end if;
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-- Mnemonic LQID ------------------------------------------------------
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-- Mnemonic LQID ------------------------------------------------------
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when MN_LQID =>
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when MN_LQID =>
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force_mc_s <= true;
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force_mc_s <= true;
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no_int_v := true;
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en_int_v := false;
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if not second_cyc_q then
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if not second_cyc_q then
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-- first cycle: push PC and set PC from A/M,
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-- first cycle: push PC and set PC from A/M,
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-- read IOL from program memory
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-- read IOL from program memory
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if cyc_v = 1 then
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if cyc_v = 1 then
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stack_op_o <= STACK_PUSH;
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stack_op_o <= STACK_PUSH;
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| Line 638... |
Line 646... |
end if;
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end if;
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-- Mnemonic LBI -------------------------------------------------------
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-- Mnemonic LBI -------------------------------------------------------
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when MN_LBI =>
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when MN_LBI =>
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is_lbi_o <= true;
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is_lbi_o <= true;
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no_int_v := true;
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en_int_v := false;
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dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
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dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
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dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
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dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
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if cyc_v = 1 and not skip_lbi_i then
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if cyc_v = 1 and not skip_lbi_i then
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-- increment Bd by 1
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-- increment Bd by 1
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b_op_o <= B_SET_B_INC;
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b_op_o <= B_SET_B_INC;
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| Line 780... |
Line 788... |
-- apply default decoder output, largest required vector
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-- apply default decoder output, largest required vector
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dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
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dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
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-- LBI
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-- LBI
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if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
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if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
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is_lbi_o <= true;
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is_lbi_o <= true;
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no_int_v := true;
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en_int_v := false;
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if cyc_v > 0 and not skip_lbi_i then
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if cyc_v > 0 and not skip_lbi_i then
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b_op_o <= B_SET_B;
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b_op_o <= B_SET_B;
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skip_op_o <= SKIP_LBI;
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skip_op_o <= SKIP_LBI;
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end if;
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end if;
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end if;
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end if;
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| Line 815... |
Line 823... |
end if;
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end if;
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-- Interrupt handling -----------------------------------------------------
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-- Interrupt handling -----------------------------------------------------
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if t420_type_v and
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if t420_type_v and
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en_q(1) = '1' and int_i and not no_int_v then
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en_q(1) = '1' and int_i and en_int_v then
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if last_cycle_s then
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if last_cycle_s then
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if cyc_v = 1 then
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if cyc_v = 1 then
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pc_op_o <= PC_INT;
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stack_op_o <= STACK_PUSH;
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stack_op_o <= STACK_PUSH;
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end if;
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end if;
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if icyc_en_i then
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if icyc_en_i then
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ack_int_s <= true;
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ack_int_s <= true;
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io_in_op_o <= IOIN_INTACK;
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io_in_op_o <= IOIN_INTACK;
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pc_op_o <= PC_INT;
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-- push skip state that was determined by current instruction
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-- push skip state that was determined by current instruction
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-- and will be valid for the next instruction which is delayed
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-- and will be valid for the next instruction which is delayed
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-- by the interrupt
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-- by the interrupt
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skip_op_o <= SKIP_PUSH;
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skip_op_o <= SKIP_PUSH;
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end if;
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end if;
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| Line 849... |
Line 857... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
|
-- File History:
|
--
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--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.4 2006/05/27 19:14:18 arniml
|
|
-- interrupt functionality added
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--
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-- Revision 1.3 2006/05/22 00:02:36 arniml
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-- Revision 1.3 2006/05/22 00:02:36 arniml
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-- instructions ININ and INIL implemented
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-- instructions ININ and INIL implemented
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--
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--
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-- Revision 1.2 2006/05/07 02:24:16 arniml
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-- Revision 1.2 2006/05/07 02:24:16 arniml
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-- fix sensitivity list
|
-- fix sensitivity list
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