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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The serial input/output unit.
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-- The serial input/output unit.
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--
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--
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-- $Id: t400_sio.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
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-- $Id: t400_sio.vhd,v 1.2 2006-05-06 13:34:58 arniml Exp $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 102... |
Line 102... |
signal dec_sio_s : boolean;
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signal dec_sio_s : boolean;
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signal new_sio_s,
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signal new_sio_s,
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sio_q : unsigned(dw_range_t);
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sio_q : unsigned(dw_range_t);
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signal skl_q : std_logic;
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signal skl_q : std_logic;
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signal phi1_en_q : std_logic;
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signal so_s,
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signal so_s,
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sk_s : std_logic;
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sk_s : std_logic;
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signal vdd_s : std_logic;
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signal vdd_s : std_logic;
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Line 124... |
seq: process (ck_i, por_i)
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seq: process (ck_i, por_i)
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begin
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begin
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if por_i then
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if por_i then
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sio_q <= (others => '0');
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sio_q <= (others => '0');
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skl_q <= '1';
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skl_q <= '1';
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phi1_en_q <= '1';
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si_q <= '1';
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si_q <= '1';
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si_flt_q <= SI_LOW_0;
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si_flt_q <= SI_LOW_0;
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si_0_ok_q <= false;
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si_0_ok_q <= false;
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si_1_ok_q <= false;
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si_1_ok_q <= false;
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elsif ck_i'event and ck_i = '1' then
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elsif ck_i'event and ck_i = '1' then
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if res_i then
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if res_i then
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-- synchronous reset upon external reset event
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-- synchronous reset upon external reset event
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skl_q <= '1';
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skl_q <= '1';
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phi1_en_q <= '1';
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else
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else
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if in_en_i then
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if in_en_i then
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-- sample asynchronous SI input
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-- sample asynchronous SI input
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si_q <= si_i;
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si_q <= si_i;
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end if;
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end if;
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Line 156... |
Line 159... |
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else
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else
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sio_q <= new_sio_s;
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sio_q <= new_sio_s;
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end if;
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end if;
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if ck_en_i then
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-- delay enable of PHI1 by one clock cycle
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-- this prevents glitches on sk_o when enabling/disabling
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-- sk_o as a clock output
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phi1_en_q <= skl_q;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process seq;
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end process seq;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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Line 265... |
Line 275... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-- Output mapping
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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sio_o <= std_logic_vector(new_sio_s);
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sio_o <= std_logic_vector(new_sio_s);
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so_s <= en3_i and (en0_i or sio_q(3));
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so_s <= en3_i and (en0_i or sio_q(3));
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sk_s <= skl_q and (en0_i or phi1_i);
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sk_s <= phi1_en_q and (en0_i or phi1_i);
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so_o <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
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so_o <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
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so_en_o <= io_en_f (en => vdd_s,
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so_en_o <= io_en_f (en => vdd_s,
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dat => so_s, opt => opt_so_output_type_g);
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dat => so_s, opt => opt_so_output_type_g);
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sk_o <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
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sk_o <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
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sk_en_o <= io_en_f (en => vdd_s,
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sk_en_o <= io_en_f (en => vdd_s,
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Line 280... |
Line 290... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
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-- import from local CVS repository, LOC_CVS_0_1
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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