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[/] [t400/] [trunk/] [rtl/] [vhdl/] [t400_sio.vhd] - Diff between revs 2 and 8

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The serial input/output unit.
-- The serial input/output unit.
--
--
-- $Id: t400_sio.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
-- $Id: t400_sio.vhd,v 1.2 2006-05-06 13:34:58 arniml Exp $
--
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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  signal dec_sio_s  : boolean;
  signal dec_sio_s  : boolean;
 
 
  signal new_sio_s,
  signal new_sio_s,
         sio_q      : unsigned(dw_range_t);
         sio_q      : unsigned(dw_range_t);
  signal skl_q      : std_logic;
  signal skl_q      : std_logic;
 
  signal phi1_en_q  : std_logic;
 
 
  signal so_s,
  signal so_s,
         sk_s       : std_logic;
         sk_s       : std_logic;
 
 
  signal vdd_s      : std_logic;
  signal vdd_s      : std_logic;
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  seq: process (ck_i, por_i)
  seq: process (ck_i, por_i)
  begin
  begin
    if    por_i then
    if    por_i then
      sio_q     <= (others => '0');
      sio_q     <= (others => '0');
      skl_q     <= '1';
      skl_q     <= '1';
 
      phi1_en_q <= '1';
      si_q      <= '1';
      si_q      <= '1';
      si_flt_q  <= SI_LOW_0;
      si_flt_q  <= SI_LOW_0;
      si_0_ok_q <= false;
      si_0_ok_q <= false;
      si_1_ok_q <= false;
      si_1_ok_q <= false;
 
 
    elsif ck_i'event and ck_i = '1' then
    elsif ck_i'event and ck_i = '1' then
      if res_i then
      if res_i then
        -- synchronous reset upon external reset event
        -- synchronous reset upon external reset event
        skl_q <= '1';
        skl_q <= '1';
 
        phi1_en_q <= '1';
      else
      else
        if in_en_i then
        if in_en_i then
          -- sample asynchronous SI input
          -- sample asynchronous SI input
          si_q      <= si_i;
          si_q      <= si_i;
        end if;
        end if;
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        else
        else
          sio_q <= new_sio_s;
          sio_q <= new_sio_s;
        end if;
        end if;
 
 
 
        if ck_en_i then
 
          -- delay enable of PHI1 by one clock cycle
 
          -- this prevents glitches on sk_o when enabling/disabling
 
          -- sk_o as a clock output
 
          phi1_en_q <= skl_q;
 
        end if;
 
 
      end if;
      end if;
    end if;
    end if;
  end process seq;
  end process seq;
  --
  --
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
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  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Output mapping
  -- Output mapping
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  sio_o   <= std_logic_vector(new_sio_s);
  sio_o   <= std_logic_vector(new_sio_s);
  so_s    <= en3_i and (en0_i or sio_q(3));
  so_s    <= en3_i and (en0_i or sio_q(3));
  sk_s    <= skl_q and (en0_i or phi1_i);
  sk_s    <= phi1_en_q and (en0_i or phi1_i);
  so_o    <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
  so_o    <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
  so_en_o <= io_en_f (en  => vdd_s,
  so_en_o <= io_en_f (en  => vdd_s,
                      dat => so_s, opt => opt_so_output_type_g);
                      dat => so_s, opt => opt_so_output_type_g);
  sk_o    <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
  sk_o    <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
  sk_en_o <= io_en_f (en  => vdd_s,
  sk_en_o <= io_en_f (en  => vdd_s,
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.1.1.1  2006/05/06 01:56:45  arniml
 
-- import from local CVS repository, LOC_CVS_0_1
 
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
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