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Known bugs of the T48 uController core
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Known bugs of the T48 uController core
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======================================
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======================================
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Version: $Date: 2004-10-25 21:37:36 $
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Version: $Date: 2005-05-04 20:20:15 $
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Release 0.5 BETA
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----------------
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*******************************************************************************
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Wrong clock applied to T0
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After executing the 'ENT0 CLK' instruction, the internal clock (XTAL divided
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by 3) should be applied to T0.
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The t48_core applies clk_i to T0. This is equal to XTAL in the current
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implementation of t8048 and others. Therefore, the clock at T0 is three times
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faster than specified.
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Fixed in:
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clock_ctrl.vhd 1.7
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t48_core.vhd 1.8
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Fix will be included in next release.
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Release 0.4 BETA
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Release 0.4 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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See above.
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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The control signals RD' and WR' are not asserted when the instructions INS A,
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The control signals RD' and WR' are not asserted when the instructions INS A,
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BUS and OUTL BUS, A are executed. The BUS is read or written but the control
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BUS and OUTL BUS, A are executed. The BUS is read or written but the control
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signals are missing.
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signals are missing.
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Fixed in:
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Fixed in:
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decoder.vhd 1.16
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decoder.vhd 1.16
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Fix will be included in next release.
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Fix will be included in next release.
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*******************************************************************************
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*******************************************************************************
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P1 constantly in push-pull mode in t8048
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P1 constantly in push-pull mode in t8048
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Port P1 is constantly driven by an active push-pull driver instead of an
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Port P1 is constantly driven by an active push-pull driver instead of an
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open-collector driver type. This inhibits using any bit of P1 in input
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open-collector driver type. This inhibits using any bit of P1 in input
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Release 0.3 BETA
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Release 0.3 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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See above.
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Line 92... |
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Release 0.2 BETA
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Release 0.2 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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See above.
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Line 133... |
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Release 0.1 BETA
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Release 0.1 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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See above.
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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