| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
|
--
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-- The testbench for t48_core.
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-- The testbench for t48_core.
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--
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--
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-- $Id: tb.vhd,v 1.9 2004-05-17 14:43:33 arniml Exp $
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-- $Id: tb.vhd,v 1.10 2004-05-21 11:24:47 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 71... |
Line 71... |
db_bus_i : in std_logic_vector(7 downto 0);
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db_bus_i : in std_logic_vector(7 downto 0);
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p2_i : in std_logic_vector(7 downto 0)
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p2_i : in std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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component lpm_rom
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|
generic (
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LPM_WIDTH : positive;
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LPM_TYPE : string := "LPM_ROM";
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LPM_WIDTHAD : positive;
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LPM_NUMWORDS : natural := 0;
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LPM_FILE : string;
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LPM_ADDRESS_CONTROL : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_HINT : string := "UNUSED"
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);
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port (
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address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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inclock : in std_logic;
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memenab : in std_logic;
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q : out std_logic_vector(LPM_WIDTH-1 downto 0)
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);
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end component;
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signal xtal_s : std_logic;
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signal xtal_s : std_logic;
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signal xtal_n_s : std_logic;
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signal xtal_n_s : std_logic;
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signal res_n_s : std_logic;
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signal res_n_s : std_logic;
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signal xtal3_s : std_logic;
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signal xtal3_s : std_logic;
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signal int_n_s : std_logic;
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signal int_n_s : std_logic;
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| Line 97... |
Line 116... |
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signal bus_s : std_logic_vector( 7 downto 0);
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signal bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal bus_dir_s : std_logic;
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signal bus_dir_s : std_logic;
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signal ext_mem_addr_s : std_logic_vector( 7 downto 0);
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signal ext_mem_addr_q : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_we_s : std_logic;
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signal ext_ram_we_q : std_logic;
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signal rd_n_s : std_logic;
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signal rd_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal ext_rom_data_s : std_logic_vector( 7 downto 0);
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signal ext_rom_addr_s : std_logic_vector(11 downto 0);
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signal tb_p1_q : std_logic_vector( 7 downto 0);
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signal tb_p1_q : std_logic_vector( 7 downto 0);
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signal tb_p2_q : std_logic_vector( 7 downto 0);
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signal tb_p2_q : std_logic_vector( 7 downto 0);
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signal ext_mem_sel_we_s : boolean;
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signal ext_mem_sel_we_q : boolean;
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signal ena_ext_ram_s : boolean;
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signal ena_ext_ram_q : boolean;
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signal ena_tb_periph_s : boolean;
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signal ena_tb_periph_q : boolean;
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signal zero_s : std_logic;
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signal zero_s : std_logic;
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signal one_s : std_logic;
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signal one_s : std_logic;
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signal zero_byte_s : std_logic_vector( 7 downto 0);
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signal zero_byte_s : std_logic_vector( 7 downto 0);
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| Line 120... |
Line 142... |
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zero_s <= '0';
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zero_s <= '0';
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one_s <= '1';
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one_s <= '1';
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zero_byte_s <= (others => '0');
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zero_byte_s <= (others => '0');
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rom_4k : syn_rom
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-----------------------------------------------------------------------------
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-- Internal ROM, 2k bytes
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-- Initialized by file t48_rom.hex.
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-----------------------------------------------------------------------------
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rom_internal_2k : lpm_rom
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generic map (
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generic map (
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address_width_g => 12
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LPM_WIDTH => 8,
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LPM_TYPE => "LPM_ROM",
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LPM_WIDTHAD => 11,
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LPM_NUMWORDS => 2 ** 11,
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LPM_FILE => "t48_rom.hex",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_HINT => "UNUSED"
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)
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)
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port map (
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port map (
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clk_i => xtal_s,
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address => rom_addr_s(10 downto 0),
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rom_addr_i => rom_addr_s,
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inclock => xtal_s,
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rom_data_o => rom_data_s
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memenab => one_s,
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q => rom_data_s
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);
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);
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-----------------------------------------------------------------------------
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-- External ROM, 2k bytes
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-- Initialized by file t48_ext_rom.hex.
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-----------------------------------------------------------------------------
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ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0);
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ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q;
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rom_external_2k : lpm_rom
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generic map (
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LPM_WIDTH => 8,
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LPM_TYPE => "LPM_ROM",
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LPM_WIDTHAD => 11,
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LPM_NUMWORDS => 2 ** 11,
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LPM_FILE => "t48_ext_rom.hex",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_HINT => "UNUSED"
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)
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port map (
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address => ext_rom_addr_s(10 downto 0),
|
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inclock => xtal_s,
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memenab => one_s,
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q => ext_rom_data_s
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);
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|
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-----------------------------------------------------------------------------
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-- Internal RAM, 256 bytes
|
|
-----------------------------------------------------------------------------
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ram_256 : syn_ram
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ram_256 : syn_ram
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generic map (
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generic map (
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address_width_g => 8
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address_width_g => 8
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)
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)
|
port map (
|
port map (
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| Line 143... |
Line 204... |
ram_data_i => ram_data_to_s,
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ram_data_i => ram_data_to_s,
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ram_we_i => ram_we_s,
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ram_we_i => ram_we_s,
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ram_data_o => ram_data_from_s
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ram_data_o => ram_data_from_s
|
);
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);
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|
|
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-----------------------------------------------------------------------------
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-- External RAM, 256 bytes
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|
-----------------------------------------------------------------------------
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ext_ram_b : syn_ram
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ext_ram_b : syn_ram
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generic map (
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generic map (
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address_width_g => 8
|
address_width_g => 8
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)
|
)
|
port map (
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port map (
|
clk_i => xtal_s,
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clk_i => xtal_s,
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res_i => res_n_s,
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res_i => res_n_s,
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ram_addr_i => ext_mem_addr_s,
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ram_addr_i => ext_mem_addr_q,
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ram_data_i => bus_s,
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ram_data_i => bus_s,
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ram_we_i => ext_ram_we_s,
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ram_we_i => ext_ram_we_q,
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ram_data_o => ext_ram_data_from_s
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ram_data_o => ext_ram_data_from_s
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);
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);
|
|
|
t48_core_b : t48_core
|
t48_core_b : t48_core
|
generic map (
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generic map (
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| Line 173... |
Line 237... |
reset_i => res_n_s,
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reset_i => res_n_s,
|
t0_i => p1_s(0),
|
t0_i => p1_s(0),
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t0_o => open,
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t0_o => open,
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t0_dir_o => open,
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t0_dir_o => open,
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int_n_i => int_n_s,
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int_n_i => int_n_s,
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ea_i => zero_s,
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ea_i => rom_addr_s(11),
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rd_n_o => rd_n_s,
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rd_n_o => rd_n_s,
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psen_n_o => psen_n_s,
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psen_n_o => psen_n_s,
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wr_n_o => wr_n_s,
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wr_n_o => wr_n_s,
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ale_o => ale_s,
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ale_o => ale_s,
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db_i => bus_s,
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db_i => bus_s,
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| Line 258... |
Line 322... |
bus_s <= t48_bus_s
|
bus_s <= t48_bus_s
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when bus_dir_s = '1' else
|
when bus_dir_s = '1' else
|
(others => 'Z');
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(others => 'Z');
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|
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bus_s <= ext_ram_data_from_s
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bus_s <= ext_ram_data_from_s
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when rd_n_s = '0' and ena_ext_ram_s else
|
when rd_n_s = '0' and ena_ext_ram_q else
|
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(others => 'Z');
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bus_s <= ext_rom_data_s
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when psen_n_s = '0' else
|
(others => 'Z');
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(others => 'Z');
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|
|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External memory access signals
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-- External memory access signals
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--
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--
|
ext_mem: process (wr_n_s,
|
ext_mem: process (wr_n_s,
|
ext_mem_addr_s,
|
ext_mem_addr_q,
|
ena_ext_ram_s,
|
ena_ext_ram_q,
|
ale_s,
|
ale_s,
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bus_s,
|
bus_s,
|
xtal_s)
|
xtal_s)
|
begin
|
begin
|
if ale_s'event and ale_s = '0' then
|
if ale_s'event and ale_s = '0' then
|
if not is_X(bus_s) then
|
if not is_X(bus_s) then
|
ext_mem_addr_s <= bus_s;
|
ext_mem_addr_q <= bus_s;
|
else
|
else
|
ext_mem_addr_s <= (others => '0');
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ext_mem_addr_q <= (others => '0');
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end if;
|
end if;
|
end if;
|
end if;
|
|
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if wr_n_s'event and wr_n_s = '1' then
|
if wr_n_s'event and wr_n_s = '1' then
|
-- write enable for external RAM
|
-- write enable for external RAM
|
if ena_ext_ram_s then
|
if ena_ext_ram_q then
|
ext_ram_we_s <= '1';
|
ext_ram_we_q <= '1';
|
end if;
|
end if;
|
|
|
-- process external memory selector
|
-- process external memory selector
|
if ext_mem_addr_s = "11111111" then
|
if ext_mem_addr_q = "11111111" then
|
ext_mem_sel_we_s <= true;
|
ext_mem_sel_we_q <= true;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
if xtal_s'event and xtal_s = '1' then
|
if xtal_s'event and xtal_s = '1' then
|
ext_ram_we_s <= '0';
|
ext_ram_we_q <= '0';
|
ext_mem_sel_we_s <= false;
|
ext_mem_sel_we_q <= false;
|
end if;
|
end if;
|
|
|
end process ext_mem;
|
end process ext_mem;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 315... |
Line 383... |
-- + testbench peripherals
|
-- + testbench peripherals
|
--
|
--
|
ext_mem_sel: process (res_n_s, xtal_s)
|
ext_mem_sel: process (res_n_s, xtal_s)
|
begin
|
begin
|
if res_n_s = '0' then
|
if res_n_s = '0' then
|
ena_ext_ram_s <= true;
|
ena_ext_ram_q <= true;
|
ena_tb_periph_s <= false;
|
ena_tb_periph_q <= false;
|
|
|
elsif xtal_s'event and xtal_s = '1' then
|
elsif xtal_s'event and xtal_s = '1' then
|
if ext_mem_sel_we_s then
|
if ext_mem_sel_we_q then
|
if bus_s(0) = '1' then
|
if bus_s(0) = '1' then
|
ena_ext_ram_s <= true;
|
ena_ext_ram_q <= true;
|
else
|
else
|
ena_ext_ram_s <= false;
|
ena_ext_ram_q <= false;
|
end if;
|
end if;
|
|
|
if bus_s(1) = '1' then
|
if bus_s(1) = '1' then
|
ena_tb_periph_s <= true;
|
ena_tb_periph_q <= true;
|
else
|
else
|
ena_tb_periph_s <= false;
|
ena_tb_periph_q <= false;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
| Line 368... |
Line 436... |
if res_n_s = '0' then
|
if res_n_s = '0' then
|
tb_p1_q <= (others => 'H');
|
tb_p1_q <= (others => 'H');
|
tb_p2_q <= (others => 'H');
|
tb_p2_q <= (others => 'H');
|
|
|
elsif wr_n_s'event and wr_n_s = '1' then
|
elsif wr_n_s'event and wr_n_s = '1' then
|
if ena_tb_periph_s then
|
if ena_tb_periph_q then
|
case ext_mem_addr_s is
|
case ext_mem_addr_q is
|
-- P1
|
-- P1
|
when "00000000" =>
|
when "00000000" =>
|
tb_p1_q <= oc_f(t48_bus_s);
|
tb_p1_q <= oc_f(t48_bus_s);
|
|
|
-- P2
|
-- P2
|
| Line 484... |
Line 552... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.9 2004/05/17 14:43:33 arniml
|
|
-- add testbench peripherals for P1 and P2
|
|
-- this became necessary to observe a difference between externally applied
|
|
-- port data and internally applied port data
|
|
--
|
-- Revision 1.8 2004/04/25 20:41:48 arniml
|
-- Revision 1.8 2004/04/25 20:41:48 arniml
|
-- connect if_timing to P2 output of T48
|
-- connect if_timing to P2 output of T48
|
--
|
--
|
-- Revision 1.7 2004/04/25 16:23:21 arniml
|
-- Revision 1.7 2004/04/25 16:23:21 arniml
|
-- added if_timing
|
-- added if_timing
|
