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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Decoder unit.
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-- The Decoder unit.
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-- It decodes the instruction opcodes and executes them.
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-- It decodes the instruction opcodes and executes them.
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--
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--
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-- $Id: decoder.vhd,v 1.7 2004-04-15 22:06:05 arniml Exp $
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-- $Id: decoder.vhd,v 1.8 2004-04-18 18:57:43 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 227... |
Line 227... |
signal retr_executed_s : boolean;
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signal retr_executed_s : boolean;
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signal int_executed_s : boolean;
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signal int_executed_s : boolean;
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signal int_pending_s : boolean;
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signal int_pending_s : boolean;
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-- pragma translate_off
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-- pragma translate_off
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signal istrobe_s : std_logic;
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signal istrobe_res_q : std_logic;
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signal istrobe_q : std_logic;
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signal injected_int_q : std_logic;
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signal injected_int_q : std_logic;
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-- pragma translate_on
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-- pragma translate_on
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begin
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begin
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Line 292... |
-- Generates the control signals that are basically needed for the
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-- Generates the control signals that are basically needed for the
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-- handling of a machine cycle.
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-- handling of a machine cycle.
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--
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--
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machine_cycle: process (clk_mstate_i,
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machine_cycle: process (clk_mstate_i,
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clk_second_cycle_i,
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clk_second_cycle_i,
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last_cycle_s,
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ea_i,
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ea_i,
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assert_psen_s,
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assert_psen_s,
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branch_taken_q,
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branch_taken_q,
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int_pending_s)
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int_pending_s)
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| Line 320... |
Line 322... |
if need_address_v and not int_pending_s then
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if need_address_v and not int_pending_s then
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if ea_i = '0' then
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if ea_i = '0' then
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pm_read_pmem_o <= true;
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pm_read_pmem_o <= true;
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else
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else
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bus_read_bus_s <= true;
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bus_read_bus_s <= true;
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p2_output_pch_o <= true;
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end if;
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end if;
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end if;
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end if;
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if not clk_second_cycle_i then
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if not clk_second_cycle_i then
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if not int_pending_s then
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if not int_pending_s then
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| Line 340... |
Line 343... |
end if;
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end if;
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when MSTATE3 =>
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when MSTATE3 =>
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if need_address_v then
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if need_address_v then
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pm_write_pmem_addr_s <= true;
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pm_write_pmem_addr_s <= true;
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end if;
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if ea_i = '1' then
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if ea_i = '1' and
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(need_address_v and last_cycle_s) then
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bus_output_pcl_o <= true;
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bus_output_pcl_o <= true;
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end if;
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end if;
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end if;
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when MSTATE4 =>
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when MSTATE4 =>
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if need_address_v and ea_i = '1' then
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if ea_i = '1' and
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(need_address_v or last_cycle_s) then
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clk_assert_psen_o <= true;
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clk_assert_psen_o <= true;
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p2_output_pch_o <= true;
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p2_output_pch_o <= true;
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bus_output_pcl_o <= true;
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end if;
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end if;
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when MSTATE5 =>
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when MSTATE5 =>
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if need_address_v and ea_i = '1' then
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if ea_i = '1' and
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(need_address_v and last_cycle_s) then
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clk_assert_psen_o <= true;
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clk_assert_psen_o <= true;
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p2_output_pch_o <= true;
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end if;
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end if;
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when others =>
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when others =>
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-- pragma translate_off
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-- pragma translate_off
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assert false
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assert false
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Line 1776... |
branch_taken_q <= false;
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branch_taken_q <= false;
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f1_q <= '0';
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f1_q <= '0';
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mb_q <= '0';
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mb_q <= '0';
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t0_dir_q <= '0';
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t0_dir_q <= '0';
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-- pragma translate_off
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-- pragma translate_off
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istrobe_s <= '0';
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istrobe_res_q <= '1';
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istrobe_q <= '0';
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injected_int_q <= '0';
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injected_int_q <= '0';
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-- pragma translate_on
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-- pragma translate_on
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elsif clk_i'event and clk_i = clk_active_c then
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if en_clk_i then
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Line 1812... |
if ent0_clk_s then
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if ent0_clk_s then
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t0_dir_q <= '1';
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t0_dir_q <= '1';
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end if;
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end if;
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-- pragma translate_off
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-- pragma translate_off
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-- Instruction Strobe -------------------------------------------------
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if clk_mstate_i = MSTATE5 and last_cycle_s and
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injected_int_q = '0' then
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istrobe_s <= '1';
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else
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istrobe_s <= '0';
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end if;
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-- Marker for injected instruction ------------------------------------
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-- Marker for injected instruction ------------------------------------
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if opc_inj_int_s then
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if opc_inj_int_s then
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injected_int_q <= '1';
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injected_int_q <= '1';
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elsif clk_mstate_i = MSTATE5 and last_cycle_s then
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elsif clk_mstate_i = MSTATE5 and last_cycle_s then
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injected_int_q <= '0';
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injected_int_q <= '0';
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end if;
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end if;
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-- Remove istrobe after reset suppression -----------------------------
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if clk_mstate_i = MSTATE5 and last_cycle_s then
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istrobe_res_q <= '0';
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end if;
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-- pragma translate_on
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-- pragma translate_on
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end if;
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end if;
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-- pragma translate_off
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-- Instruction Strobe ---------------------------------------------------
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if clk_mstate_i = MSTATE5 and last_cycle_s and
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injected_int_q = '0' then
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if istrobe_res_q = '0' then
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istrobe_q <= '1';
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end if;
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else
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istrobe_q <= '0';
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end if;
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-- pragma translate_on
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end if;
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end if;
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end process regs;
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end process regs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- pragma translate_off
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-- pragma translate_off
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-- assign to global signal for testbench
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-- assign to global signal for testbench
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tb_istrobe_s <= istrobe_s;
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tb_istrobe_s <= istrobe_q;
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-- pragma translate_on
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-- pragma translate_on
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping.
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-- Output Mapping.
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| Line 1856... |
Line 1873... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
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-- Revision 1.7 2004/04/15 22:06:05 arniml
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-- + add marker for injected calls
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-- + suppress intstruction strobes for injected calls
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--
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-- Revision 1.6 2004/04/14 20:53:33 arniml
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-- Revision 1.6 2004/04/14 20:53:33 arniml
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-- make istrobe visible through testbench package
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-- make istrobe visible through testbench package
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--
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--
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-- Revision 1.5 2004/04/07 22:09:03 arniml
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-- Revision 1.5 2004/04/07 22:09:03 arniml
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-- remove unused signals
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-- remove unused signals
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