URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] [verif/] [black_box/] [rb/] [int/] [test.asm] - Diff between revs 12 and 57

Rev 12	Rev 57
Line 1...	Line 1...
`;; *******************************************************************`	`;; *******************************************************************`
`;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $`	`;; $Id: test.asm,v 1.2 2004-04-15 22:01:51 arniml Exp $`
`;;`	`;;`
`;; Test interrupts in conjunction with RB-switching.`	`;; Test interrupts in conjunction with RB-switching.`
`;; *******************************************************************`	`;; *******************************************************************`

`INCLUDE "cpu.inc"`	`INCLUDE "cpu.inc"`
Line 121...	Line 121...
`jnz fail_p3`	`jnz fail_p3`
`mov a, r7`	`mov a, r7`
`jnz fail_p3`	`jnz fail_p3`
`ret`	`ret`

	`;; synchronize on interrupt`
	`;; use r7 for timeout detection`
`sync_on_int:`	`sync_on_int:`
`jni wait_int2`	`mov a, r7 ; save r7`
`jmp sync_on_int`	`mov r7, #000H`
	`wait_int1:`
	`jni sync_on_int2`
	`djnz r7, wait_int1`
	`jmp fail_p3`

	`sync_on_int2:`
	`mov r7, #000H`
`wait_int2:`	`wait_int2:`
`jni wait_int2`	`jni still_int`
	`mov r7, a ; restore r7`
`call clr_int`	`call clr_int`
`retr`	`retr`
	`still_int:`
	`djnz r7, wait_int2`
	`jmp fail_p3`

`clr_int:`	`clr_int:`
`;; clear latched interrupt request with RETR!`	`;; clear latched interrupt request with RETR!`
`retr`	`retr`