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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t48_core.
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-- The testbench for t48_core.
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--
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--
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-- $Id: tb.vhd,v 1.7 2004-04-25 16:23:21 arniml Exp $
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-- $Id: tb.vhd,v 1.8 2004-04-25 20:41:48 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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psen_n_i => psen_n_s,
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psen_n_i => psen_n_s,
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rd_n_i => rd_n_s,
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rd_n_i => rd_n_s,
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wr_n_i => wr_n_s,
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wr_n_i => wr_n_s,
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prog_n_i => prog_n_s,
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prog_n_i => prog_n_s,
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db_bus_i => bus_s,
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db_bus_i => bus_s,
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p2_i => p2_s
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p2_i => t48_p2_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Port logic
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-- Port logic
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2004/04/25 16:23:21 arniml
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-- added if_timing
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--
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-- Revision 1.6 2004/04/14 20:57:44 arniml
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-- Revision 1.6 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- wait for instruction strobe after final end-of-simulation detection
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-- this ensures that the last mov instruction is part of the dump and
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-- this ensures that the last mov instruction is part of the dump and
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-- enables 100% matching with i8039 simulator
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-- enables 100% matching with i8039 simulator
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--
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--
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