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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Arithmetic Logic Unit (ALU).
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-- The Arithmetic Logic Unit (ALU).
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-- It contains the ALU core plus the Accumulator and the Temp Reg.
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-- It contains the ALU core plus the Accumulator and the Temp Reg.
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--
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--
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-- $Id: alu.vhd,v 1.3 2004-04-04 14:18:52 arniml Exp $
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-- $Id: alu.vhd,v 1.4 2004-04-06 18:10:41 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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signal in_a_s,
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signal in_a_s,
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in_b_s : word_t;
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in_b_s : word_t;
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-- output of the ALU core
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-- output of the ALU core
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signal data_s : word_t;
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signal data_s : word_t;
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signal add_result_s : alu_operand_t;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process working_regs
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-- Process working_regs
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--
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--
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-- All operations defined in alu_op_t are handled here.
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-- All operations defined in alu_op_t are handled here.
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--
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--
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alu_core: process (in_a_s,
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alu_core: process (in_a_s,
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in_b_s,
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in_b_s,
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alu_op_i,
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alu_op_i,
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use_carry_i,
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add_result_s)
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carry_i,
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aux_carry_i)
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variable add_v : alu_operand_t;
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variable c_v : std_logic;
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function add_f(a, b : alu_operand_t;
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c : std_logic ) return alu_operand_t is
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begin
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return UNSIGNED(a) + UNSIGNED(b) + CONV_UNSIGNED(c, alu_operand_t'length);
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end;
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begin
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begin
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-- default assigments
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-- default assigments
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data_s <= (others => '0');
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data_s <= (others => '0');
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carry_o <= '0';
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carry_o <= '0';
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when ALU_XOR =>
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when ALU_XOR =>
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data_s <= in_a_s xor in_b_s;
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data_s <= in_a_s xor in_b_s;
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-- Operation: Add -------------------------------------------------------
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-- Operation: Add -------------------------------------------------------
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when ALU_ADD =>
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when ALU_ADD =>
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if use_carry_i then
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data_s <= add_result_s(data_s'range);
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c_v := carry_i;
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carry_o <= add_result_s(add_result_s'high);
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else
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c_v := '0';
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end if;
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add_v := add_f("0" & in_a_s, "0" & in_b_s, c_v);
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data_s <= add_v(data_s'range);
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carry_o <= add_v(add_v'high);
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-- Operation: CPL -------------------------------------------------------
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-- Operation: CPL -------------------------------------------------------
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when ALU_CPL =>
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when ALU_CPL =>
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data_s <= not in_a_s;
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data_s <= not in_a_s;
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data_s(3 downto 0) <= in_a_s(7 downto 4);
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data_s(3 downto 0) <= in_a_s(7 downto 4);
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data_s(7 downto 4) <= in_a_s(3 downto 0);
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data_s(7 downto 4) <= in_a_s(3 downto 0);
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-- Operation: DEC -------------------------------------------------------
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-- Operation: DEC -------------------------------------------------------
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when ALU_DEC =>
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when ALU_DEC =>
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add_v := add_f(not ("0" & in_a_s), "000000001", '0');
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data_s <= add_result_s(data_s'range);
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data_s <= not add_v(data_s'range);
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-- Operation: INC -------------------------------------------------------
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-- Operation: INC -------------------------------------------------------
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when ALU_INC =>
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when ALU_INC =>
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add_v := add_f("0" & in_a_s, "000000001", '0');
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data_s <= add_result_s(data_s'range);
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data_s <= add_v(data_s'range);
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-- Operation CONCAT -----------------------------------------------------
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-- Operation CONCAT -----------------------------------------------------
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when ALU_CONCAT =>
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when ALU_CONCAT =>
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data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
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data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process aux_carry
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-- Process adder
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--
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--
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-- Purpose:
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-- Purpose:
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-- Calculates the Auxiliary Carry.
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-- Implements the adder used by several instructions.
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-- This way of modelling the adder forces resource sharing of:
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-- * ADD
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-- * INC
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-- * DEC
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--
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--
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aux_carry: process (in_a_s,
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adder: process (in_a_s,
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in_b_s,
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in_b_s,
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data_s)
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alu_op_i,
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carry_i,
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use_carry_i)
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variable add_a_v, add_b_v : alu_operand_t;
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variable result_v : alu_operand_t;
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variable c_v : std_logic;
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variable aux_c_v : std_logic_vector(1 downto 0);
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variable aux_c_v : std_logic_vector(1 downto 0);
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begin
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begin
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aux_carry_o <= '0';
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-- Carry Selection --------------------------------------------------------
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if use_carry_i then
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c_v := carry_i;
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else
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c_v := '0';
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end if;
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-- Operand Selection ------------------------------------------------------
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-- defaults for ADD
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add_a_v := '0' & in_a_s;
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add_b_v := '0' & in_b_s;
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case alu_op_i is
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when ALU_INC =>
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add_b_v := "000000001";
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when ALU_DEC =>
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add_b_v := "111111111";
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when others =>
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null;
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end case;
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-- The Adder --------------------------------------------------------------
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result_v := UNSIGNED(add_a_v) +
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UNSIGNED(add_b_v) +
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CONV_UNSIGNED(c_v, alu_operand_t'length);
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add_result_s <= result_v;
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-- Auxiliary Carry --------------------------------------------------------
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aux_c_v := in_a_s(4) & in_b_s(4);
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aux_c_v := in_a_s(4) & in_b_s(4);
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case aux_c_v is
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case aux_c_v is
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when "00" | "11" =>
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when "00" | "11" =>
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if data_s(4) = '1' then
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if result_v(4) = '1' then
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aux_carry_o <= '1';
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aux_carry_o <= '1';
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end if;
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end if;
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when "01" | "10" =>
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when "01" | "10" =>
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if data_s(4) = '0' then
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if result_v(4) = '0' then
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aux_carry_o <= '1';
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aux_carry_o <= '1';
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end if;
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end if;
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when others =>
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when others =>
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aux_carry_o <= '0';
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null;
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null;
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end case;
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end case;
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end process aux_carry;
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end process adder;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/04/04 14:18:52 arniml
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-- add measures to implement XCHD
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--
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-- Revision 1.2 2004/03/28 21:08:51 arniml
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-- Revision 1.2 2004/03/28 21:08:51 arniml
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-- support for DA instruction
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-- support for DA instruction
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--
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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-- initial check-in
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