| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Program Status Word (PSW).
|
-- The Program Status Word (PSW).
|
-- Implements the PSW with its special bits.
|
-- Implements the PSW with its special bits.
|
--
|
--
|
-- $Id: psw.vhd,v 1.5 2004-04-24 11:25:39 arniml Exp $
|
-- $Id: psw.vhd,v 1.6 2004-04-24 23:44:25 arniml Exp $
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
| Line 78... |
Line 78... |
|
|
end psw;
|
end psw;
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_arith.all;
|
use ieee.numeric_std.all;
|
|
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.nibble_t;
|
use work.t48_pack.nibble_t;
|
| Line 180... |
Line 180... |
if read_psw_i then
|
if read_psw_i then
|
data_o(7 downto 4) <= psw_q;
|
data_o(7 downto 4) <= psw_q;
|
end if;
|
end if;
|
|
|
if read_sp_i then
|
if read_sp_i then
|
data_o(3 downto 0) <= '1' & conv_std_logic_vector(sp_q, 3);
|
data_o(3 downto 0) <= '1' & std_logic_vector(sp_q);
|
end if;
|
end if;
|
|
|
end process data_out;
|
end process data_out;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 193... |
Line 193... |
-- pragma translate_off
|
-- pragma translate_off
|
tb: process (psw_q, sp_q)
|
tb: process (psw_q, sp_q)
|
begin
|
begin
|
psw_s(7 downto 4) <= psw_q;
|
psw_s(7 downto 4) <= psw_q;
|
psw_s(3) <= '1';
|
psw_s(3) <= '1';
|
psw_s(2 downto 0) <= conv_std_logic_vector(sp_q, 3);
|
psw_s(2 downto 0) <= std_logic_vector(sp_q);
|
end process tb;
|
end process tb;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output mapping.
|
-- Output mapping.
|
| Line 212... |
Line 212... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.5 2004/04/24 11:25:39 arniml
|
|
-- removed dummy_s - workaround not longer needed for GHDL 0.11.1
|
|
--
|
-- Revision 1.4 2004/04/18 18:59:01 arniml
|
-- Revision 1.4 2004/04/18 18:59:01 arniml
|
-- add temporary workaround for GHDL 0.11
|
-- add temporary workaround for GHDL 0.11
|
--
|
--
|
-- Revision 1.3 2004/04/04 14:15:45 arniml
|
-- Revision 1.3 2004/04/04 14:15:45 arniml
|
-- add dump_compare support
|
-- add dump_compare support
|
