| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T48 Microcontroller Core
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-- T48 Microcontroller Core
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--
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--
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-- $Id: t48_core.vhd,v 1.3 2004-03-28 21:27:50 arniml Exp $
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-- $Id: t48_core.vhd,v 1.4 2004-03-29 19:39:58 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 97... |
Line 97... |
db_o : out std_logic_vector( 7 downto 0);
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db_o : out std_logic_vector( 7 downto 0);
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db_dir_o : out std_logic;
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db_dir_o : out std_logic;
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t1_i : in std_logic;
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t1_i : in std_logic;
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p2_i : in std_logic_vector( 7 downto 0);
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p2_i : in std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2_limp_o : out std_logic;
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p2_low_imp_o : out std_logic;
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p1_i : in std_logic_vector( 7 downto 0);
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p1_i : in std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_limp_o : out std_logic;
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p1_low_imp_o : out std_logic;
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prog_n_o : out std_logic;
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prog_n_o : out std_logic;
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-- Core Interface ---------------------------------------------------------
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-- Core Interface ---------------------------------------------------------
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clk_i : in std_logic;
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clk_i : in std_logic;
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en_clk_i : in std_logic;
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en_clk_i : in std_logic;
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xtal3_o : out std_logic;
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xtal3_o : out std_logic;
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| Line 528... |
Line 528... |
write_p1_i => p1_write_p1_s,
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write_p1_i => p1_write_p1_s,
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read_p1_i => p1_read_p1_s,
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read_p1_i => p1_read_p1_s,
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read_reg_i => p1_read_reg_s,
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read_reg_i => p1_read_reg_s,
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p1_i => p1_i,
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p1_i => p1_i,
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p1_o => p1_o,
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p1_o => p1_o,
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p1_limp_o => p1_limp_o
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p1_low_imp_o => p1_low_imp_o
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);
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);
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end generate;
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end generate;
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|
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skip_p1: if include_port1_g = 0 generate
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skip_p1: if include_port1_g = 0 generate
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p1_data_s <= (others => bus_idle_level_c);
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p1_data_s <= (others => bus_idle_level_c);
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p1_o <= (others => '0');
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p1_o <= (others => '0');
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p1_limp_o <= '0';
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p1_low_imp_o <= '0';
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end generate;
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end generate;
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|
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use_p2: if include_port2_g = 1 generate
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use_p2: if include_port2_g = 1 generate
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p2_b : p2
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p2_b : p2
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port map (
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port map (
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| Line 556... |
Line 556... |
output_pch_i => p2_output_pch_s,
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output_pch_i => p2_output_pch_s,
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output_exp_i => p2_output_exp_s,
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output_exp_i => p2_output_exp_s,
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pch_i => pmem_addr_s(11 downto 8),
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pch_i => pmem_addr_s(11 downto 8),
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p2_i => p2_i,
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p2_i => p2_i,
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p2_o => p2_o,
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p2_o => p2_o,
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p2_limp_o => p2_limp_o
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p2_low_imp_o => p2_low_imp_o
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);
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);
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end generate;
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end generate;
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|
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skip_p2: if include_port2_g = 0 generate
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skip_p2: if include_port2_g = 0 generate
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p2_data_s <= (others => bus_idle_level_c);
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p2_data_s <= (others => bus_idle_level_c);
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p2_o <= (others => '0');
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p2_o <= (others => '0');
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p2_limp_o <= '0';
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p2_low_imp_o <= '0';
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end generate;
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end generate;
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|
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pmem_ctrl_b : pmem_ctrl
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pmem_ctrl_b : pmem_ctrl
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port map (
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port map (
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clk_i => clk_i,
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clk_i => clk_i,
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| Line 630... |
Line 630... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/03/28 21:27:50 arniml
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-- update wiring for DA support
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--
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-- Revision 1.2 2004/03/28 13:13:20 arniml
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-- Revision 1.2 2004/03/28 13:13:20 arniml
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-- connect control signal for Port 2 expander
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-- connect control signal for Port 2 expander
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--
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--
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- initial check-in
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-- initial check-in
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