| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The testbench for t48_core.
|
-- The testbench for t48_core.
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--
|
--
|
-- $Id: tb.vhd,v 1.2 2004-03-24 23:22:35 arniml Exp $
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-- $Id: tb.vhd,v 1.3 2004-03-26 22:39:28 arniml Exp $
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--
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--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
|
-- All rights reserved
|
-- All rights reserved
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--
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--
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| Line 315... |
Line 315... |
wait on tb_accu_s;
|
wait on tb_accu_s;
|
if tb_accu_s = "01010101" then
|
if tb_accu_s = "01010101" then
|
wait on tb_accu_s;
|
wait on tb_accu_s;
|
if tb_accu_s = "00000001" then
|
if tb_accu_s = "00000001" then
|
assert false
|
assert false
|
report "Simulation PASS."
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report "Simulation Result: PASS."
|
severity note;
|
severity note;
|
else
|
else
|
assert false
|
assert false
|
report "Simulation FAIL."
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report "Simulation Result: FAIL."
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severity note;
|
severity note;
|
end if;
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end if;
|
|
|
assert false
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assert false
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report "End of simulation reached."
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report "End of simulation reached."
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| Line 342... |
Line 342... |
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2004/03/24 23:22:35 arniml
|
|
-- put ext_ram on falling clock edge to sample the write enable properly
|
|
--
|
-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- Revision 1.1 2004/03/24 21:42:10 arniml
|
-- initial check-in
|
-- initial check-in
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--
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--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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No newline at end of file
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No newline at end of file
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