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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t48_core.
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-- The testbench for t48_core.
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--
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--
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-- $Id: tb.vhd,v 1.6 2004-04-14 20:57:44 arniml Exp $
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-- $Id: tb.vhd,v 1.7 2004-04-25 16:23:21 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 58... |
Line 58... |
architecture behav of tb is
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architecture behav of tb is
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-- clock period, 11 MHz
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-- clock period, 11 MHz
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constant period_c : time := 90 ns;
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constant period_c : time := 90 ns;
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component if_timing
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port(
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xtal_i : in std_logic;
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ale_i : in std_logic;
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psen_n_i : in std_logic;
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rd_n_i : in std_logic;
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wr_n_i : in std_logic;
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prog_n_i : in std_logic;
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db_bus_i : in std_logic_vector(7 downto 0);
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p2_i : in std_logic_vector(7 downto 0)
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);
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end component;
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signal xtal_s : std_logic;
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signal xtal_s : std_logic;
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signal xtal_n_s : std_logic;
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signal xtal_n_s : std_logic;
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signal res_n_s : std_logic;
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signal res_n_s : std_logic;
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signal xtal3_s : std_logic;
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signal xtal3_s : std_logic;
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signal int_n_s : std_logic;
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signal int_n_s : std_logic;
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| Line 77... |
Line 90... |
signal t48_p1_s : std_logic_vector( 7 downto 0);
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signal t48_p1_s : std_logic_vector( 7 downto 0);
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signal p1_low_imp_s : std_logic;
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signal p1_low_imp_s : std_logic;
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signal p2_s : std_logic_vector( 7 downto 0);
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signal p2_s : std_logic_vector( 7 downto 0);
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signal t48_p2_s : std_logic_vector( 7 downto 0);
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signal t48_p2_s : std_logic_vector( 7 downto 0);
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signal p2_low_imp_s : std_logic;
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signal p2_low_imp_s : std_logic;
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signal psen_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal bus_s : std_logic_vector( 7 downto 0);
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signal bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal bus_dir_s : std_logic;
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signal bus_dir_s : std_logic;
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| Line 154... |
Line 168... |
t0_o => open,
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t0_o => open,
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t0_dir_o => open,
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t0_dir_o => open,
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int_n_i => int_n_s,
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int_n_i => int_n_s,
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ea_i => zero_s,
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ea_i => zero_s,
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rd_n_o => rd_n_s,
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rd_n_o => rd_n_s,
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psen_n_o => open,
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psen_n_o => psen_n_s,
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wr_n_o => wr_n_s,
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wr_n_o => wr_n_s,
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ale_o => ale_s,
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ale_o => ale_s,
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db_i => bus_s,
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db_i => bus_s,
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db_o => t48_bus_s,
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db_o => t48_bus_s,
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db_dir_o => bus_dir_s,
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db_dir_o => bus_dir_s,
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| Line 179... |
Line 193... |
dmem_data_o => ram_data_to_s,
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dmem_data_o => ram_data_to_s,
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pmem_addr_o => rom_addr_s,
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pmem_addr_o => rom_addr_s,
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pmem_data_i => rom_data_s
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pmem_data_i => rom_data_s
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);
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);
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if_timing_b : if_timing
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port map (
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xtal_i => xtal_s,
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ale_i => ale_s,
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psen_n_i => psen_n_s,
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rd_n_i => rd_n_s,
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wr_n_i => wr_n_s,
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prog_n_i => prog_n_s,
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db_bus_i => bus_s,
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p2_i => p2_s
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Port logic
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-- Port logic
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--
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--
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ports: process (t48_p1_s,
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ports: process (t48_p1_s,
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| Line 347... |
Line 373... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.6 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- this ensures that the last mov instruction is part of the dump and
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-- enables 100% matching with i8039 simulator
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--
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-- Revision 1.5 2004/03/29 19:45:15 arniml
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-- Revision 1.5 2004/03/29 19:45:15 arniml
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-- rename pX_limp to pX_low_imp
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-- rename pX_limp to pX_low_imp
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--
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--
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-- Revision 1.4 2004/03/28 21:30:25 arniml
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-- Revision 1.4 2004/03/28 21:30:25 arniml
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-- connect prog_n_o
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-- connect prog_n_o
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