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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t8048.
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-- The testbench for t8048.
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--
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--
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-- $Id: tb_t8048.vhd,v 1.3 2004-04-14 20:57:44 arniml Exp $
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-- $Id: tb_t8048.vhd,v 1.4 2004-04-18 19:00:58 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 89... |
signal ram_data_to_s : std_logic_vector( 7 downto 0);
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signal ram_data_to_s : std_logic_vector( 7 downto 0);
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signal ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ram_addr_s : std_logic_vector( 7 downto 0);
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signal ram_addr_s : std_logic_vector( 7 downto 0);
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signal ram_we_s : std_logic;
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signal ram_we_s : std_logic;
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signal t0_s : std_logic;
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signal t1_s : std_logic;
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal ext_ram_addr_s : std_logic_vector( 7 downto 0);
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signal ext_ram_addr_s : std_logic_vector( 7 downto 0);
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Line 107... |
begin
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begin
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zero_s <= '0';
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zero_s <= '0';
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one_s <= '1';
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one_s <= '1';
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t0_s <= 'H';
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t1_s <= 'H';
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p2_b <= (others => 'H');
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p2_b <= (others => 'H');
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p1_b <= (others => 'H');
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p1_b <= (others => 'H');
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ext_ram_b : syn_ram
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ext_ram_b : syn_ram
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generic map (
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generic map (
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Line 127... |
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t8048_b : t8048
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t8048_b : t8048
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port map (
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port map (
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xtal_i => xtal_s,
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xtal_i => xtal_s,
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reset_n_i => res_n_s,
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reset_n_i => res_n_s,
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t0_b => t0_s,
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t0_b => p1_b(0),
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int_n_i => int_n_s,
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int_n_i => int_n_s,
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ea_i => zero_s,
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ea_i => zero_s,
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rd_n_o => rd_n_s,
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rd_n_o => rd_n_s,
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psen_n_o => psen_n_s,
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psen_n_o => psen_n_s,
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wr_n_o => wr_n_s,
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wr_n_o => wr_n_s,
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ale_o => ale_s,
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ale_o => ale_s,
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db_b => db_b,
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db_b => db_b,
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t1_i => t1_s,
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t1_i => p1_b(1),
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p2_b => p2_b,
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p2_b => p2_b,
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p1_b => p1_b,
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p1_b => p1_b,
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prog_n_o => prog_n_s
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prog_n_o => prog_n_s
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);
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);
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Line 147... |
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External RAM access signals
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-- External RAM access signals
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--
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--
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ext_ram: process (wr_n_s,
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ext_ram: process (wr_n_s,
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ext_ram_addr_s,
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ale_s,
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ale_s,
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db_b)
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db_b)
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-- clk_s)
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begin
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begin
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if ale_s'event and ale_s = '0' then
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if ale_s'event and ale_s = '0' then
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if not is_X(db_b) then
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if not is_X(db_b) then
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ext_ram_addr_s <= db_b;
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ext_ram_addr_s <= db_b;
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else
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else
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Line 257... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- this ensures that the last mov instruction is part of the dump and
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-- enables 100% matching with i8039 simulator
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--
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-- Revision 1.2 2004/03/26 22:39:28 arniml
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-- Revision 1.2 2004/03/26 22:39:28 arniml
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-- enhance simulation result string
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-- enhance simulation result string
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--
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--
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-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- initial check-in
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-- initial check-in
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