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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Decoder unit.
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-- The Decoder unit.
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-- It decodes the instruction opcodes and executes them.
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-- It decodes the instruction opcodes and executes them.
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--
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--
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-- $Id: decoder.vhd,v 1.13 2004-05-20 21:51:40 arniml Exp $
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-- $Id: decoder.vhd,v 1.14 2004-06-30 21:18:28 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 228... |
Line 228... |
signal dis_i_s : boolean;
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signal dis_i_s : boolean;
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signal tim_int_s : boolean;
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signal tim_int_s : boolean;
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signal retr_executed_s : boolean;
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signal retr_executed_s : boolean;
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signal int_executed_s : boolean;
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signal int_executed_s : boolean;
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signal int_pending_s : boolean;
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signal int_pending_s : boolean;
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signal int_in_progress_s : boolean;
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|
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-- pragma translate_off
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-- pragma translate_off
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signal istrobe_res_q : std_logic;
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signal istrobe_res_q : std_logic;
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signal istrobe_q : std_logic;
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signal istrobe_q : std_logic;
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signal injected_int_q : std_logic;
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signal injected_int_q : std_logic;
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Line 281... |
dis_i_i => dis_i_s,
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dis_i_i => dis_i_s,
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ext_int_o => open,
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ext_int_o => open,
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tim_int_o => tim_int_s,
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tim_int_o => tim_int_s,
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retr_executed_i => retr_executed_s,
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retr_executed_i => retr_executed_s,
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int_executed_i => int_executed_s,
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int_executed_i => int_executed_s,
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int_pending_o => int_pending_s
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int_pending_o => int_pending_s,
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int_in_progress_o => int_in_progress_s
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);
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);
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last_cycle_s <= not opc_multi_cycle_s or
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last_cycle_s <= not opc_multi_cycle_s or
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(opc_multi_cycle_s and clk_second_cycle_i);
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(opc_multi_cycle_s and clk_second_cycle_i);
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Line 405... |
psw_carry_i,
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psw_carry_i,
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psw_f0_i,
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psw_f0_i,
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f1_q,
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f1_q,
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mb_q,
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mb_q,
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tim_int_s,
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tim_int_s,
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int_pending_s)
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int_pending_s,
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int_in_progress_s)
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procedure address_indirect_3_f is
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procedure address_indirect_3_f is
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begin
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begin
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-- apply dmem address from selected register for indirect mode
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-- apply dmem address from selected register for indirect mode
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if opc_opcode_s(3) = '0' or enable_quartus_bugfix_c then
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if opc_opcode_s(3) = '0' or enable_quartus_bugfix_c then
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Line 443... |
pm_write_pcl_o <= true;
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pm_write_pcl_o <= true;
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branch_taken_s <= true;
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branch_taken_s <= true;
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-- end if;
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-- end if;
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end;
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end;
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-- intermediate value of the Program Memory Bank Flag
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variable mb_v : std_logic;
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begin
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begin
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-- default assignments
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-- default assignments
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data_s <= (others => '-');
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data_s <= (others => '-');
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read_dec_s <= false;
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read_dec_s <= false;
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branch_taken_s <= false;
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branch_taken_s <= false;
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Line 521... |
int_executed_s <= false;
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int_executed_s <= false;
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add_write_pmem_addr_s <= false;
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add_write_pmem_addr_s <= false;
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ent0_clk_s <= false;
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ent0_clk_s <= false;
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add_read_bus_s <= false;
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add_read_bus_s <= false;
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-- the Program Memory Bank Flag is held low when interrupts are in progress
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-- according to the MCS-48 User's Manual
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if int_in_progress_s then
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mb_v := '0';
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else
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mb_v := mb_q;
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end if;
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-- prepare potential register indirect address mode
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-- prepare potential register indirect address mode
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if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then
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if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then
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data_s <= (others => '0');
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data_s <= (others => '0');
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if opc_opcode_s(3) = '1' then
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if opc_opcode_s(3) = '1' then
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data_s(2 downto 0) <= opc_opcode_s(2 downto 0);
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data_s(2 downto 0) <= opc_opcode_s(2 downto 0);
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Line 764... |
when MSTATE2 =>
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when MSTATE2 =>
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pm_write_pch_o <= true;
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pm_write_pch_o <= true;
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read_dec_s <= true;
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read_dec_s <= true;
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if not int_pending_s then
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if not int_pending_s then
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-- store high part of target address in Program Counter
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-- store high part of target address in Program Counter
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data_s <= "0000" & mb_q & opc_opcode_s(7 downto 5);
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data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5);
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else
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else
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-- apply high part of vector address manually
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-- apply high part of vector address manually
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data_s <= (others => '0');
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data_s <= (others => '0');
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int_executed_s <= true;
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int_executed_s <= true;
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end if;
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end if;
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Line 1108... |
pm_write_pcl_o <= true;
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pm_write_pcl_o <= true;
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branch_taken_s <= true;
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branch_taken_s <= true;
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-- store high part of target address in Program Counter
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-- store high part of target address in Program Counter
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when MSTATE2 =>
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when MSTATE2 =>
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data_s <= "0000" & mb_q & opc_opcode_s(7 downto 5);
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data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5);
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read_dec_s <= true;
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read_dec_s <= true;
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pm_write_pch_o <= true;
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pm_write_pch_o <= true;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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Line 1944... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.13 2004/05/20 21:51:40 arniml
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-- clean-up use of ea_i
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--
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-- Revision 1.12 2004/05/17 14:40:09 arniml
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-- Revision 1.12 2004/05/17 14:40:09 arniml
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-- assert p2_read_p2_o when expander port is read
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-- assert p2_read_p2_o when expander port is read
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--
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--
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-- Revision 1.11 2004/05/16 15:33:39 arniml
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-- Revision 1.11 2004/05/16 15:33:39 arniml
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-- work around bug in Quartus II 4.0
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-- work around bug in Quartus II 4.0
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