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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Decoder unit.
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-- The Decoder unit.
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-- It decodes the instruction opcodes and executes them.
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-- It decodes the instruction opcodes and executes them.
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--
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--
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-- $Id: decoder.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
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-- $Id: decoder.vhd,v 1.2 2004-03-28 13:06:32 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 86... |
Line 86... |
p1_write_p1_o : out boolean;
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p1_write_p1_o : out boolean;
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p1_read_p1_o : out boolean;
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p1_read_p1_o : out boolean;
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p2_write_p2_o : out boolean;
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p2_write_p2_o : out boolean;
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p2_write_exp_o : out boolean;
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p2_write_exp_o : out boolean;
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p2_read_p2_o : out boolean;
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p2_read_p2_o : out boolean;
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p2_read_exp_o : out boolean;
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pm_write_pcl_o : out boolean;
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pm_write_pcl_o : out boolean;
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pm_read_pcl_o : out boolean;
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pm_read_pcl_o : out boolean;
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pm_write_pch_o : out boolean;
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pm_write_pch_o : out boolean;
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pm_read_pch_o : out boolean;
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pm_read_pch_o : out boolean;
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pm_read_pmem_o : out boolean;
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pm_read_pmem_o : out boolean;
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Line 292... |
pm_inc_pc_s <= false;
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pm_inc_pc_s <= false;
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pm_write_pmem_addr_s <= false;
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pm_write_pmem_addr_s <= false;
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pm_read_pmem_o <= false;
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pm_read_pmem_o <= false;
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bus_output_pcl_o <= false;
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bus_output_pcl_o <= false;
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p2_output_pch_o <= false;
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p2_output_pch_o <= false;
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p2_output_exp_o <= false;
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opc_read_bus_s <= false;
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opc_read_bus_s <= false;
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opc_inj_int_s <= false;
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opc_inj_int_s <= false;
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bus_read_bus_s <= false;
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bus_read_bus_s <= false;
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need_address_v := not clk_second_cycle_i or
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need_address_v := not clk_second_cycle_i or
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Line 466... |
p1_read_reg_o <= false;
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p1_read_reg_o <= false;
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p2_write_p2_o <= false;
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p2_write_p2_o <= false;
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p2_write_exp_o <= false;
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p2_write_exp_o <= false;
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p2_read_p2_o <= false;
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p2_read_p2_o <= false;
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p2_read_reg_o <= false;
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p2_read_reg_o <= false;
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p2_read_exp_o <= false;
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p2_output_exp_o <= false;
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psw_special_data_o <= '0';
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psw_special_data_o <= '0';
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psw_inc_stackp_o <= false;
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psw_inc_stackp_o <= false;
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psw_dec_stackp_o <= false;
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psw_dec_stackp_o <= false;
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psw_write_carry_o <= false;
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psw_write_carry_o <= false;
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psw_write_aux_carry_o <= false;
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psw_write_aux_carry_o <= false;
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Line 1205... |
tim_read_timer_o <= true; -- MOV A, T
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tim_read_timer_o <= true; -- MOV A, T
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alu_write_accu_o <= true;
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alu_write_accu_o <= true;
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end if;
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end if;
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end if;
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end if;
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-- Mnemonic OUTD_PP_A ---------------------------------------------------
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when MN_OUTD_PP_A =>
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clk_assert_prog_o <= true;
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if not clk_second_cycle_i then
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case clk_mstate_i is
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-- propagate expander port number to Port 2
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when MSTATE3 =>
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data_s(7 downto 4) <= (others => '0');
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data_s(1 downto 0) <= opc_opcode_s(1 downto 0);
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-- decide which 8243 command to use
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case opc_opcode_s(7 downto 4) is
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when "1001" =>
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data_s(3 downto 2) <= "11"; -- ANLD command
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when "1000" =>
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data_s(3 downto 2) <= "10"; -- ORLD command
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when "0011" =>
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data_s(3 downto 2) <= "01"; -- MOVD command
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when others =>
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null;
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end case;
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read_dec_s <= true;
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p2_write_exp_o <= true;
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-- output expander port number on Port 2 while active edge of PROG
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-- write Accumulator to expander port
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when MSTATE4 =>
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p2_output_exp_o <= true;
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alu_read_alu_o <= true;
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p2_write_exp_o <= true;
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when MSTATE5 =>
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p2_output_exp_o <= true;
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when others =>
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null;
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end case;
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else
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-- hold expander port until inactive edge of PROG
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if clk_mstate_i = MSTATE1 or clk_mstate_i = MSTATE2 then
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p2_output_exp_o <= true;
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end if;
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end if;
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-- Mnemonic MOVD_A_PP ---------------------------------------------------
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when MN_MOVD_A_PP =>
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clk_assert_prog_o <= true;
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if not clk_second_cycle_i then
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case clk_mstate_i is
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-- propagate expander port number to Port 2
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when MSTATE3 =>
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data_s <= "0000" &
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"00" & -- 8243 command: read
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opc_opcode_s(1 downto 0);
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read_dec_s <= true;
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p2_write_exp_o <= true;
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-- output expander port number on Port 2 while active edge of PROG
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-- write 1's to expander port to set lower nibble of Port 2 to input
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when MSTATE4 =>
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p2_output_exp_o <= true;
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data_s(nibble_t'range) <= (others => '1');
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read_dec_s <= true;
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p2_write_exp_o <= true;
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when MSTATE5 =>
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p2_output_exp_o <= true;
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when others =>
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null;
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end case;
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else
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case clk_mstate_i is
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-- hold expander port until inactive edge of PROG
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when MSTATE1 =>
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p2_output_exp_o <= true;
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-- hold expander port until inactive edge of PROG
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-- write Accumulator with nibble of expander port
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when MSTATE2 =>
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p2_output_exp_o <= true;
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p2_read_exp_o <= true;
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alu_write_accu_o <= true;
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when others =>
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null;
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end case;
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end if;
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-- Mnemonic MOVP --------------------------------------------------------
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-- Mnemonic MOVP --------------------------------------------------------
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when MN_MOVP =>
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when MN_MOVP =>
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assert_psen_s <= true;
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assert_psen_s <= true;
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if not clk_second_cycle_i then
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if not clk_second_cycle_i then
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Line 1757... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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