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[/] [t48/] [tags/] [rel_0_5_beta/] [bench/] [vhdl/] [tb.vhd] - Diff between revs 8 and 10

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Rev 8 Rev 10
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The testbench for t48_core.
-- The testbench for t48_core.
--
--
-- $Id: tb.vhd,v 1.1 2004-03-24 21:42:10 arniml Exp $
-- $Id: tb.vhd,v 1.2 2004-03-24 23:22:35 arniml Exp $
--
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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  -- clock period, 11 MHz
  -- clock period, 11 MHz
  constant period_c : time := 90 ns;
  constant period_c : time := 90 ns;
 
 
  signal xtal_s          : std_logic;
  signal xtal_s          : std_logic;
 
  signal xtal_n_s        : std_logic;
  signal res_n_s         : std_logic;
  signal res_n_s         : std_logic;
  signal xtal3_s         : std_logic;
  signal xtal3_s         : std_logic;
  signal int_n_s         : std_logic;
  signal int_n_s         : std_logic;
  signal ale_s           : std_logic;
  signal ale_s           : std_logic;
  signal rom_addr_s      : std_logic_vector(11 downto 0);
  signal rom_addr_s      : std_logic_vector(11 downto 0);
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    if wr_n_s'event and wr_n_s = '1' then
    if wr_n_s'event and wr_n_s = '1' then
      ext_ram_we_s <= '1';
      ext_ram_we_s <= '1';
    end if;
    end if;
 
 
    if xtal_s'event then
    if xtal_s'event and xtal_s = '1' then
      ext_ram_we_s <= '0';
      ext_ram_we_s <= '0';
    end if;
    end if;
 
 
  end process ext_ram;
  end process ext_ram;
  --
  --
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
 
  xtal_n_s <= not xtal_s;
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- The clock generator
  -- The clock generator
  --
  --
  clk_gen: process
  clk_gen: process
  begin
  begin
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.1  2004/03/24 21:42:10  arniml
 
-- initial check-in
 
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
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