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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The testbench for t48_core.
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-- The testbench for t48_core.
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--
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--
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-- $Id: tb.vhd,v 1.8 2004-04-25 20:41:48 arniml Exp $
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-- $Id: tb.vhd,v 1.9 2004-05-17 14:43:33 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 97... |
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signal bus_s : std_logic_vector( 7 downto 0);
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signal bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal t48_bus_s : std_logic_vector( 7 downto 0);
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signal bus_dir_s : std_logic;
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signal bus_dir_s : std_logic;
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signal ext_ram_addr_s : std_logic_vector( 7 downto 0);
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signal ext_mem_addr_s : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_we_s : std_logic;
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signal ext_ram_we_s : std_logic;
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signal rd_n_s : std_logic;
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signal rd_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal tb_p1_q : std_logic_vector( 7 downto 0);
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signal tb_p2_q : std_logic_vector( 7 downto 0);
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signal ext_mem_sel_we_s : boolean;
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signal ena_ext_ram_s : boolean;
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signal ena_tb_periph_s : boolean;
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signal zero_s : std_logic;
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signal zero_s : std_logic;
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signal one_s : std_logic;
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signal one_s : std_logic;
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signal zero_byte_s : std_logic_vector( 7 downto 0);
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signal zero_byte_s : std_logic_vector( 7 downto 0);
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begin
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begin
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Line 150... |
address_width_g => 8
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address_width_g => 8
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)
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)
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port map (
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port map (
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clk_i => xtal_s,
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clk_i => xtal_s,
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res_i => res_n_s,
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res_i => res_n_s,
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ram_addr_i => ext_ram_addr_s,
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ram_addr_i => ext_mem_addr_s,
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ram_data_i => bus_s,
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ram_data_i => bus_s,
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ram_we_i => ext_ram_we_s,
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ram_we_i => ext_ram_we_s,
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ram_data_o => ext_ram_data_from_s
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ram_data_o => ext_ram_data_from_s
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);
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);
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Line 258... |
bus_s <= t48_bus_s
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bus_s <= t48_bus_s
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when bus_dir_s = '1' else
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when bus_dir_s = '1' else
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(others => 'Z');
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(others => 'Z');
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bus_s <= ext_ram_data_from_s
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bus_s <= ext_ram_data_from_s
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when rd_n_s = '0' else
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when rd_n_s = '0' and ena_ext_ram_s else
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(others => 'Z');
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(others => 'Z');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External RAM access signals
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-- External memory access signals
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--
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--
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ext_ram: process (wr_n_s,
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ext_mem: process (wr_n_s,
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ext_ram_addr_s,
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ext_mem_addr_s,
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ena_ext_ram_s,
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ale_s,
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ale_s,
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bus_s,
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bus_s,
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xtal_s)
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xtal_s)
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begin
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begin
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if ale_s'event and ale_s = '0' then
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if ale_s'event and ale_s = '0' then
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if not is_X(bus_s) then
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if not is_X(bus_s) then
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ext_ram_addr_s <= bus_s;
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ext_mem_addr_s <= bus_s;
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else
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else
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ext_ram_addr_s <= (others => '0');
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ext_mem_addr_s <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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if wr_n_s'event and wr_n_s = '1' then
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if wr_n_s'event and wr_n_s = '1' then
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-- write enable for external RAM
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if ena_ext_ram_s then
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ext_ram_we_s <= '1';
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ext_ram_we_s <= '1';
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end if;
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end if;
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-- process external memory selector
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if ext_mem_addr_s = "11111111" then
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ext_mem_sel_we_s <= true;
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end if;
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end if;
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if xtal_s'event and xtal_s = '1' then
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if xtal_s'event and xtal_s = '1' then
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ext_ram_we_s <= '0';
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ext_ram_we_s <= '0';
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ext_mem_sel_we_s <= false;
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end if;
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end if;
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end process ext_ram;
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end process ext_mem;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process ext_mem_sel
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--
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-- Purpose:
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-- Select external memory address space.
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-- This is either
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-- + external RAM
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-- + testbench peripherals
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--
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ext_mem_sel: process (res_n_s, xtal_s)
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begin
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if res_n_s = '0' then
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ena_ext_ram_s <= true;
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ena_tb_periph_s <= false;
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elsif xtal_s'event and xtal_s = '1' then
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if ext_mem_sel_we_s then
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if bus_s(0) = '1' then
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ena_ext_ram_s <= true;
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else
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ena_ext_ram_s <= false;
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end if;
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if bus_s(1) = '1' then
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ena_tb_periph_s <= true;
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else
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ena_tb_periph_s <= false;
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end if;
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end if;
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end if;
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end process ext_mem_sel;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process tb_periph
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--
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-- Purpose:
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-- Implements the testbenc peripherals driving P1 and P2.
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--
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tb_periph: process (res_n_s, wr_n_s)
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function oc_f (pX : std_logic_vector) return std_logic_vector is
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variable r_v : std_logic_vector(pX'range);
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begin
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for i in pX'range loop
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if pX(i) = '0' then
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r_v(i) := '0';
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else
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r_v(i) := 'H';
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end if;
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end loop;
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return r_v;
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end;
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begin
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if res_n_s = '0' then
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tb_p1_q <= (others => 'H');
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tb_p2_q <= (others => 'H');
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elsif wr_n_s'event and wr_n_s = '1' then
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if ena_tb_periph_s then
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case ext_mem_addr_s is
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-- P1
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when "00000000" =>
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tb_p1_q <= oc_f(t48_bus_s);
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-- P2
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when "00000001" =>
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tb_p2_q <= oc_f(t48_bus_s);
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when others =>
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null;
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end case;
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end if;
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end if;
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end process tb_periph;
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--
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-----------------------------------------------------------------------------
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p1_s <= tb_p1_q;
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p2_s <= tb_p2_q;
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xtal_n_s <= not xtal_s;
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xtal_n_s <= not xtal_s;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- The clock generator
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-- The clock generator
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--
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--
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| Line 373... |
Line 484... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.8 2004/04/25 20:41:48 arniml
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-- connect if_timing to P2 output of T48
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--
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-- Revision 1.7 2004/04/25 16:23:21 arniml
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-- Revision 1.7 2004/04/25 16:23:21 arniml
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-- added if_timing
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-- added if_timing
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--
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--
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-- Revision 1.6 2004/04/14 20:57:44 arniml
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-- Revision 1.6 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- wait for instruction strobe after final end-of-simulation detection
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