| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Clock Control unit.
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-- The Clock Control unit.
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-- Clock States and Machine Cycles are generated here.
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-- Clock States and Machine Cycles are generated here.
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--
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--
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-- $Id: clock_ctrl.vhd,v 1.4 2004-04-24 23:44:25 arniml Exp $
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-- $Id: clock_ctrl.vhd,v 1.5 2004-10-25 19:35:41 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 207... |
Line 207... |
if xtal3_s then
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if xtal3_s then
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psen_q <= false;
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psen_q <= false;
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end if;
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end if;
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when MSTATE2 =>
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when MSTATE2 =>
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if xtal2_s then
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if xtal3_s then
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-- RD, WR are removed at the end of XTAL3 of second machine cycle
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-- RD, WR are removed at the end of XTAL3 of second machine cycle
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rd_q <= false;
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rd_q <= false;
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wr_q <= false;
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wr_q <= false;
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-- PROG is removed at the and of XTAL3 of second machine cycle
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-- PROG is removed at the and of XTAL3 of second machine cycle
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prog_q <= false;
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prog_q <= false;
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| Line 378... |
Line 378... |
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
|
-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2004/04/24 23:44:25 arniml
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|
-- move from std_logic_arith to numeric_std
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--
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-- Revision 1.3 2004/04/18 18:56:23 arniml
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-- Revision 1.3 2004/04/18 18:56:23 arniml
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-- reset machine state to MSTATE3 to allow proper instruction fetch
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-- reset machine state to MSTATE3 to allow proper instruction fetch
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-- after reset
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-- after reset
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--
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--
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-- Revision 1.2 2004/03/28 12:55:06 arniml
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-- Revision 1.2 2004/03/28 12:55:06 arniml
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