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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Decoder unit.
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-- The Decoder unit.
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-- It decodes the instruction opcodes and executes them.
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-- It decodes the instruction opcodes and executes them.
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--
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--
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-- $Id: decoder.vhd,v 1.6 2004-04-14 20:53:33 arniml Exp $
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-- $Id: decoder.vhd,v 1.7 2004-04-15 22:06:05 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 228... |
signal int_executed_s : boolean;
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signal int_executed_s : boolean;
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signal int_pending_s : boolean;
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signal int_pending_s : boolean;
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-- pragma translate_off
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-- pragma translate_off
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signal istrobe_s : std_logic;
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signal istrobe_s : std_logic;
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signal injected_int_q : std_logic;
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-- pragma translate_on
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-- pragma translate_on
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 1769... |
Line 1770... |
f1_q <= '0';
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f1_q <= '0';
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mb_q <= '0';
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mb_q <= '0';
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t0_dir_q <= '0';
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t0_dir_q <= '0';
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-- pragma translate_off
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-- pragma translate_off
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istrobe_s <= '0';
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istrobe_s <= '0';
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injected_int_q <= '0';
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-- pragma translate_on
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-- pragma translate_on
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elsif clk_i'event and clk_i = clk_active_c then
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if en_clk_i then
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-- T0 direction selection
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-- T0 direction selection
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if ent0_clk_s then
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if ent0_clk_s then
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t0_dir_q <= '1';
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t0_dir_q <= '1';
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end if;
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end if;
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end if;
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-- pragma translate_off
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-- pragma translate_off
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-- Instruction Strobe ---------------------------------------------------
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-- Instruction Strobe -------------------------------------------------
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if clk_mstate_i = MSTATE5 and last_cycle_s then
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if clk_mstate_i = MSTATE5 and last_cycle_s and
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injected_int_q = '0' then
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istrobe_s <= '1';
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istrobe_s <= '1';
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else
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else
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istrobe_s <= '0';
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istrobe_s <= '0';
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end if;
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end if;
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-- Marker for injected instruction ------------------------------------
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if opc_inj_int_s then
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injected_int_q <= '1';
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elsif clk_mstate_i = MSTATE5 and last_cycle_s then
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injected_int_q <= '0';
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end if;
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-- pragma translate_on
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-- pragma translate_on
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end if;
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end if;
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end if;
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end process regs;
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end process regs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- pragma translate_off
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-- pragma translate_off
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Line 1856... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.6 2004/04/14 20:53:33 arniml
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-- make istrobe visible through testbench package
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--
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-- Revision 1.5 2004/04/07 22:09:03 arniml
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-- Revision 1.5 2004/04/07 22:09:03 arniml
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-- remove unused signals
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-- remove unused signals
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--
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--
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-- Revision 1.4 2004/04/04 14:18:53 arniml
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-- Revision 1.4 2004/04/04 14:18:53 arniml
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-- add measures to implement XCHD
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-- add measures to implement XCHD
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