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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Port 2 unit.
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-- The Port 2 unit.
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-- Implements the Port 2 logic.
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-- Implements the Port 2 logic.
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--
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--
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-- $Id: p2.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
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-- $Id: p2.vhd,v 1.2 2004-03-28 13:11:43 arniml Exp $
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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| Line 60... |
Line 60... |
data_o : out word_t;
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data_o : out word_t;
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write_p2_i : in boolean;
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write_p2_i : in boolean;
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write_exp_i : in boolean;
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write_exp_i : in boolean;
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read_p2_i : in boolean;
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read_p2_i : in boolean;
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read_reg_i : in boolean;
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read_reg_i : in boolean;
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read_exp_i : in boolean;
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-- Port 2 Interface -------------------------------------------------------
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-- Port 2 Interface -------------------------------------------------------
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output_pch_i : in boolean;
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output_pch_i : in boolean;
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output_exp_i : in boolean;
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output_exp_i : in boolean;
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pch_i : in nibble_t;
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pch_i : in nibble_t;
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p2_i : in word_t;
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p2_i : in word_t;
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| Line 82... |
Line 83... |
use work.t48_pack.res_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.bus_idle_level_c;
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architecture rtl of p2 is
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architecture rtl of p2 is
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subtype exp_t is std_logic_vector(1 downto 0);
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-- 8243 expander address mapping
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type exp_array_t is array (3 downto 0) of nibble_t;
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constant exp_c : exp_array_t := ("0100", "0101", "0110", "0111");
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-- the port output register
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-- the port output register
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signal p2_q : word_t;
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signal p2_q : word_t;
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-- the low impedance marker
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-- the low impedance marker
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signal limp_q : std_logic;
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signal limp_q : std_logic;
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-- the expander register
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-- the expander register
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signal exp_q : exp_t;
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signal exp_q : nibble_t;
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signal exp_s : nibble_t;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process p2_regs
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-- Process p2_regs
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| Line 136... |
Line 130... |
end process p2_regs;
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end process p2_regs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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exp_s <= exp_c(conv_integer(unsigned(exp_q)));
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-----------------------------------------------------------------------------
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-- Process p2_port
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--
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-- Purpose:
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-- Generates the output byte vector for Port 2.
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--
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p2_port: process (p2_q,
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exp_q,
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output_exp_i,
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pch_i,
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output_pch_i)
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begin
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p2_o <= p2_q;
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if output_exp_i then
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p2_o(nibble_t'range) <= exp_q;
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end if;
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if output_pch_i then
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p2_o(nibble_t'range) <= pch_i;
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end if;
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end process p2_port;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process p2_data
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--
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-- Purpose:
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-- Generates the T48 bus data.
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--
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p2_data: process (read_p2_i,
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p2_i,
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read_reg_i,
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p2_q,
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read_exp_i)
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begin
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data_o <= (others => bus_idle_level_c);
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if read_p2_i then
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data_o <= p2_i;
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elsif read_reg_i then
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data_o <= p2_q;
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elsif read_exp_i then
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data_o <= "0000" & p2_i(nibble_t'range);
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end if;
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end process p2_data;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping.
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-- Output Mapping.
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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p2_o <= "0000" & exp_s
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when output_exp_i else
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"0000" & pch_i
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when output_pch_i else
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p2_q;
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p2_limp_o <= limp_q;
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p2_limp_o <= limp_q;
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data_o <= (others => bus_idle_level_c)
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when not read_p2_i else
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p2_q
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when read_reg_i else
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p2_i;
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end rtl;
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end rtl;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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