URL
https://opencores.org/ocsvn/t48/t48/trunk
[/] [t48/] [tags/] [rel_0_6_1_beta/] [KNOWN_BUGS] - Diff between revs 109 and 117
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 109 |
Rev 117 |
| Line 1... |
Line 1... |
|
|
Known bugs of the T48 uController core
|
Known bugs of the T48 uController core
|
======================================
|
======================================
|
Version: $Date: 2004-05-20 22:00:59 $
|
Version: $Date: 2004-06-29 20:41:52 $
|
|
|
|
|
|
Release 0.2 BETA
|
|
----------------
|
|
|
|
*******************************************************************************
|
|
Program Memory bank can be switched during interrupt
|
|
|
|
During an interrupt service routine (i.e. after vectoring to location 3 or 7
|
|
of the Program Memory and befor executing the RETR instruction) the Program
|
|
Memory bank can be switched by executing a JMP or CALL instruction. These
|
|
instructions honour the current state of the Program Memory Bank Flag and thus
|
|
switch the Program Memory bank upon execution.
|
|
|
|
|
|
|
Release 0.1 BETA
|
Release 0.1 BETA
|
----------------
|
----------------
|
|
|
|
*******************************************************************************
|
|
Program Memory bank can be switched during interrupt
|
|
|
|
See above.
|
|
|
******************************************************************************
|
******************************************************************************
|
External Program Memory ignored when EA = 0
|
External Program Memory ignored when EA = 0
|
|
|
The external Program Memory is always ignored when EA = 0 with the t8048 system
|
The external Program Memory is always ignored when EA = 0 with the t8048 system
|
toplevel. Desired behaviour is to access external Program Memory when code
|
toplevel. Desired behaviour is to access external Program Memory when code
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.