| Line 1... |
Line 1... |
|
|
Known bugs of the T48 uController core
|
Known bugs of the T48 uController core
|
======================================
|
======================================
|
Version: $Date: 2004-10-24 09:13:06 $
|
Version: $Date: 2004-10-25 21:37:36 $
|
|
|
|
|
Release 0.4 BETA
|
Release 0.4 BETA
|
----------------
|
----------------
|
|
|
*******************************************************************************
|
*******************************************************************************
|
|
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
|
|
|
|
The control signals RD' and WR' are not asserted when the instructions INS A,
|
|
BUS and OUTL BUS, A are executed. The BUS is read or written but the control
|
|
signals are missing.
|
|
|
|
Fixed in:
|
|
decoder.vhd 1.16
|
|
Fix will be included in next release.
|
|
|
|
|
|
*******************************************************************************
|
P1 constantly in push-pull mode in t8048
|
P1 constantly in push-pull mode in t8048
|
|
|
Port P1 is constantly driven by an active push-pull driver instead of an
|
Port P1 is constantly driven by an active push-pull driver instead of an
|
open-collector driver type. This inhibits using any bit of P1 in input
|
open-collector driver type. This inhibits using any bit of P1 in input
|
direction.
|
direction.
|
| Line 22... |
Line 34... |
|
|
Release 0.3 BETA
|
Release 0.3 BETA
|
----------------
|
----------------
|
|
|
*******************************************************************************
|
*******************************************************************************
|
|
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
|
|
|
|
See above.
|
|
|
|
*******************************************************************************
|
P1 constantly in push-pull mode in t8048
|
P1 constantly in push-pull mode in t8048
|
|
|
See above.
|
See above.
|
|
|
*******************************************************************************
|
*******************************************************************************
|
| Line 47... |
Line 64... |
|
|
Release 0.2 BETA
|
Release 0.2 BETA
|
----------------
|
----------------
|
|
|
*******************************************************************************
|
*******************************************************************************
|
|
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
|
|
|
|
See above.
|
|
|
|
*******************************************************************************
|
P1 constantly in push-pull mode in t8048
|
P1 constantly in push-pull mode in t8048
|
|
|
See above.
|
See above.
|
|
|
*******************************************************************************
|
*******************************************************************************
|
| Line 78... |
Line 100... |
|
|
Release 0.1 BETA
|
Release 0.1 BETA
|
----------------
|
----------------
|
|
|
*******************************************************************************
|
*******************************************************************************
|
|
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
|
|
|
|
See above.
|
|
|
|
*******************************************************************************
|
PSENn Timing
|
PSENn Timing
|
|
|
See above.
|
See above.
|
|
|
*******************************************************************************
|
*******************************************************************************
|
