| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Interrupt Controller.
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-- The Interrupt Controller.
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-- It collects the interrupt sources and notifies the decoder.
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-- It collects the interrupt sources and notifies the decoder.
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--
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--
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-- $Id: int.vhd,v 1.5 2005-09-13 21:00:16 arniml Exp $
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-- $Id: int.vhd,v 1.6 2005-11-01 21:26:24 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 53... |
Line 53... |
|
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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en_clk_i : in boolean;
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xtal_i : in std_logic;
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clk_mstate_i : in mstate_t;
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clk_mstate_i : in mstate_t;
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jtf_executed_i : in boolean;
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jtf_executed_i : in boolean;
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tim_overflow_i : in boolean;
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tim_overflow_i : in boolean;
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tf_o : out std_logic;
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tf_o : out std_logic;
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en_tcnti_i : in boolean;
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en_tcnti_i : in boolean;
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| Line 155... |
Line 156... |
begin
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begin
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if res_i = res_active_c then
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if res_i = res_active_c then
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timer_flag_q <= false;
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timer_flag_q <= false;
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timer_overflow_q <= false;
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timer_overflow_q <= false;
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timer_int_enable_q <= false;
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timer_int_enable_q <= false;
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int_q <= false;
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int_enable_q <= false;
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int_enable_q <= false;
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ale_q <= false;
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int_type_q <= '0';
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int_type_q <= '0';
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int_state_q <= IDLE;
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int_state_q <= IDLE;
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int_in_progress_q <= false;
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int_in_progress_q <= false;
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|
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elsif clk_i'event and clk_i = clk_active_c then
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if en_clk_i then
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|
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ale_q <= ale_i;
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|
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int_state_q <= int_state_s;
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int_state_q <= int_state_s;
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|
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if jtf_executed_i then
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if jtf_executed_i then
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timer_flag_q <= false;
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timer_flag_q <= false;
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elsif tim_overflow_i then
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elsif tim_overflow_i then
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| Line 188... |
Line 185... |
timer_int_enable_q <= false;
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timer_int_enable_q <= false;
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elsif en_tcnti_i then
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elsif en_tcnti_i then
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timer_int_enable_q <= true;
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timer_int_enable_q <= true;
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end if;
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end if;
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|
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if last_cycle_i and
|
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ale_q and not ale_i then
|
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int_q <= not to_boolean(int_n_i);
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end if;
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|
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if dis_i_i then
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if dis_i_i then
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int_enable_q <= false;
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int_enable_q <= false;
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elsif en_i_i then
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elsif en_i_i then
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int_enable_q <= true;
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int_enable_q <= true;
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end if;
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end if;
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| Line 219... |
Line 211... |
--
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--
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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|
|
|
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
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-- Process xtal_regs
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--
|
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-- Purpose:
|
|
-- Implements the sequential registers clocked with XTAL.
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--
|
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xtal_regs: process (res_i, xtal_i)
|
|
begin
|
|
if res_i = res_active_c then
|
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int_q <= false;
|
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ale_q <= false;
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|
|
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elsif xtal_i'event and xtal_i = clk_active_c then
|
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ale_q <= ale_i;
|
|
|
|
if last_cycle_i and
|
|
ale_q and not ale_i then
|
|
int_q <= not to_boolean(int_n_i);
|
|
end if;
|
|
|
|
|
|
end if;
|
|
end process xtal_regs;
|
|
--
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
-- Output Mapping.
|
-- Output Mapping.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
tf_o <= to_stdLogic(timer_flag_q);
|
tf_o <= to_stdLogic(timer_flag_q);
|
ext_int_o <= int_type_q = ext_int_c;
|
ext_int_o <= int_type_q = ext_int_c;
|
tim_int_o <= int_type_q = tim_int_c;
|
tim_int_o <= int_type_q = tim_int_c;
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| Line 234... |
Line 253... |
|
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-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.5 2005/09/13 21:00:16 arniml
|
|
-- Fix bug reports:
|
|
-- "Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
|
|
-- "Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
|
|
-- int_in_progress_o was active one cycle before int_pending_o is
|
|
-- asserted. this confused the mb multiplexer which determines the state of
|
|
-- the memory bank selection flag
|
|
--
|
-- Revision 1.4 2005/06/11 10:08:43 arniml
|
-- Revision 1.4 2005/06/11 10:08:43 arniml
|
-- introduce prefix 't48_' for all packages, entities and configurations
|
-- introduce prefix 't48_' for all packages, entities and configurations
|
--
|
--
|
-- Revision 1.3 2004/07/11 16:51:33 arniml
|
-- Revision 1.3 2004/07/11 16:51:33 arniml
|
-- cleanup copyright notice
|
-- cleanup copyright notice
|
