| Line 2... |
Line 2... |
#
|
#
|
# ############################################################################
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# ############################################################################
|
#
|
#
|
# run_regression.pl
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# run_regression.pl
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#
|
#
|
# $Id: run_regression.pl,v 1.6 2004-05-17 14:44:02 arniml Exp $
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# $Id: run_regression.pl,v 1.7 2004-07-04 12:05:55 arniml Exp $
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#
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#
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# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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#
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#
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# All rights reserved
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# All rights reserved
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#
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#
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| Line 45... |
Line 45... |
my %options;
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my %options;
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my (@asm_files, $asm_file);
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my (@asm_files, $asm_file);
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my (%cells, $cell, $cell_dir, $tag);
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my (%cells, $cell, $cell_dir, $tag);
|
my $pwd;
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my $pwd;
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my $dump_compare = 0;
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my $dump_compare = 0;
|
|
my $dump_compare_cell = 0;
|
|
|
|
|
##############################################################################
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##############################################################################
|
# Commands to call the different VHDL simulators.
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# Commands to call the different VHDL simulators.
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#
|
#
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| Line 94... |
Line 95... |
$cell_dir = "$ENV{'VERIF_DIR'}/$cell";
|
$cell_dir = "$ENV{'VERIF_DIR'}/$cell";
|
|
|
if (chdir($cell_dir)) {
|
if (chdir($cell_dir)) {
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print("Processing $cell\n");
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print("Processing $cell\n");
|
|
|
|
$dump_compare_cell = -e 'no_dump_compare' ? 0 : $dump_compare;
|
|
|
system('sh', '-c', 'rm -f $SIM_DIR/t48_rom.hex');
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system('sh', '-c', 'rm -f $SIM_DIR/t48_rom.hex');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell clean');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell clean');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell simu clean');
|
system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell simu clean');
|
if ($? == 0) {
|
if ($? == 0) {
|
chdir($ENV{'SIM_DIR'});
|
chdir($ENV{'SIM_DIR'});
|
system('sh', '-c', 'ls -l t48_rom.hex');
|
system('sh', '-c', 'ls -l t48_rom.hex');
|
system('sh', '-c', $dump_compare > 0 ? $vhdl_simulator_vcd : $vhdl_simulator);
|
system('sh', '-c', $dump_compare_cell > 0 ? $vhdl_simulator_vcd : $vhdl_simulator);
|
|
|
if ($dump_compare) {
|
if ($dump_compare_cell) {
|
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump');
|
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump');
|
system('sh', '-c',
|
system('sh', '-c',
|
'vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump');
|
'vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump');
|
system('sh', '-c', 'i8039 -f t48_rom.hex -d > dump');
|
system('sh', '-c', 'i8039 -f t48_rom.hex -x t48_ext_rom.hex -d > dump');
|
system('sh', '-c', 'egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump');
|
system('sh', '-c', 'egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump');
|
system('sh', '-c', 'diff -b -q sim.dump vhdl.dump');
|
system('sh', '-c', 'diff -b -q sim.dump vhdl.dump');
|
print("Dump Compare: ");
|
print("Dump Compare: ");
|
if ($? == 0) {
|
if ($? == 0) {
|
print("PASS\n");
|
print("PASS\n");
|
} else {
|
} else {
|
print("FAIL\n");
|
print("FAIL\n");
|
}
|
}
|
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump temp.vcd');
|
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump temp.vcd');
|
|
} elsif ($dump_compare) {
|
|
print("Dump Compare: Excluded\n");
|
}
|
}
|
|
|
} else {
|
} else {
|
print("Error: Cannot make cell $cell!\n");
|
print("Error: Cannot make cell $cell!\n");
|
}
|
}
|
