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[/] [t48/] [tags/] [rel_0_6__beta/] [rtl/] [vhdl/] [decoder.vhd] - Diff between revs 101 and 106

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- The Decoder unit.
-- The Decoder unit.
-- It decodes the instruction opcodes and executes them.
-- It decodes the instruction opcodes and executes them.
--
--
-- $Id: decoder.vhd,v 1.12 2004-05-17 14:40:09 arniml Exp $
-- $Id: decoder.vhd,v 1.13 2004-05-20 21:51:40 arniml Exp $
--
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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          pm_inc_pc_s       <= true;
          pm_inc_pc_s       <= true;
        end if;
        end if;
 
 
      when MSTATE3 =>
      when MSTATE3 =>
        if need_address_v then
        if need_address_v then
 
          -- Theory of operation:
 
          -- Program Memory address is updated at end of State 3 (or end of
 
          -- State 2 in case of a RET). Address information is thus available
 
          -- latest with State 4.
 
          -- This is the time where we need information about access target
 
          -- (internal or external = EA). EA information needs to be stable
 
          -- until end of State 1.
          pm_write_pmem_addr_s <= true;
          pm_write_pmem_addr_s <= true;
        end if;
        end if;
 
 
        if ea_i = '1' and
 
           (need_address_v and last_cycle_s) then
 
          bus_output_pcl_o   <= true;
 
        end if;
 
 
 
      when MSTATE4 =>
      when MSTATE4 =>
        if ea_i = '1' and
        if ea_i = '1' and
           (need_address_v or last_cycle_s) then
           (need_address_v or last_cycle_s) then
          clk_assert_psen_o <= true;
          clk_assert_psen_o <= true;
          p2_output_pch_o   <= true;
          p2_output_pch_o   <= true;
          bus_output_pcl_o  <= true;
          bus_output_pcl_o  <= true;
        end if;
        end if;
 
 
      when MSTATE5 =>
      when MSTATE5 =>
        if ea_i = '1' and
        if ea_i = '1' and
           (need_address_v and last_cycle_s) then
           (need_address_v or last_cycle_s) then
          clk_assert_psen_o <= true;
 
          p2_output_pch_o   <= true;
          p2_output_pch_o   <= true;
        end if;
        end if;
 
 
      when others =>
      when others =>
        -- pragma translate_off
        -- pragma translate_off
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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.12  2004/05/17 14:40:09  arniml
 
-- assert p2_read_p2_o when expander port is read
 
--
-- Revision 1.11  2004/05/16 15:33:39  arniml
-- Revision 1.11  2004/05/16 15:33:39  arniml
-- work around bug in Quartus II 4.0
-- work around bug in Quartus II 4.0
--
--
-- Revision 1.10  2004/04/25 16:22:03  arniml
-- Revision 1.10  2004/04/25 16:22:03  arniml
-- adjust external timing of BUS
-- adjust external timing of BUS

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