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[/] [t48/] [tags/] [rel_0_6__beta/] [rtl/] [vhdl/] [system/] [syn_ram-lpm-a.vhd] - Diff between revs 45 and 183

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-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- A synchronous parametrizable RAM instantiating a standard RAM from
-- A synchronous parametrizable RAM instantiating a standard RAM from
-- the Altera LPM.
-- the Altera LPM.
--
--
-- $Id: syn_ram-lpm-a.vhd,v 1.2 2004-04-07 22:09:08 arniml Exp $
-- $Id: syn_ram-lpm-a.vhd,v 1.3 2005-09-07 17:39:34 arniml Exp $
--
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
--
-- All rights reserved
-- All rights reserved
--
--
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    port (
    port (
      data                : in  std_logic_vector(LPM_WIDTH-1 downto 0);
      data                : in  std_logic_vector(LPM_WIDTH-1 downto 0);
      address             : in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
      address             : in  std_logic_vector(LPM_WIDTHAD-1 downto 0);
      we                  : in  std_logic;
      we                  : in  std_logic;
      inclock             : in  std_logic;
      inclock             : in  std_logic;
 
      outclock            : in  std_logic;
      q                   : out std_logic_vector(LPM_WIDTH-1 downto 0)
      q                   : out std_logic_vector(LPM_WIDTH-1 downto 0)
    );
    );
  end component;
  end component;
 
 
 
  signal zero_s : std_logic;
 
 
begin
begin
 
 
 
  zero_s <= '0';
 
 
  ram_b : lpm_ram_dq
  ram_b : lpm_ram_dq
    generic map (
    generic map (
      LPM_WIDTH           => 8,
      LPM_WIDTH           => 8,
      LPM_TYPE            => "LPM_RAM_DQ",
      LPM_TYPE            => "LPM_RAM_DQ",
      LPM_WIDTHAD         => address_width_g,
      LPM_WIDTHAD         => address_width_g,
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    port map (
    port map (
      data     => ram_data_i,
      data     => ram_data_i,
      address  => ram_addr_i,
      address  => ram_addr_i,
      we       => ram_we_i,
      we       => ram_we_i,
      inclock  => clk_i,
      inclock  => clk_i,
 
      outclock => zero_s,               -- unused
      q        => ram_data_o
      q        => ram_data_o
    );
    );
 
 
end lpm;
end lpm;
 
 
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File History:
-- File History:
--
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- Revision 1.2  2004/04/07 22:09:08  arniml
 
-- remove unused signals
 
--
-- Revision 1.1  2004/03/24 21:32:27  arniml
-- Revision 1.1  2004/03/24 21:32:27  arniml
-- initial check-in
-- initial check-in
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
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