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Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T48 Microcontroller Core
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-- T48 Microcontroller Core
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--
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--
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-- $Id: t48_core.vhd,v 1.2 2004-03-28 13:13:20 arniml Exp $
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-- $Id: t48_core.vhd,v 1.3 2004-03-28 21:27:50 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 45... |
-- =============
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-- =============
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--
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--
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-- Compared to the original MCS-48 architecture, the following limitations
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-- Compared to the original MCS-48 architecture, the following limitations
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-- apply:
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-- apply:
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--
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--
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-- * DA A instruction not implemented.
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-- * Nibble-wide instructions addressing expander port implemented but
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-- Implementation targeted for Beta milestone.
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-- not verified yet.
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--
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-- * Nibble-wide instructions addressing expander port not implemented.
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-- Implementation targeted for Beta milestone.
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--
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--
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-- * Single-step mode not implemented.
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-- * Single-step mode not implemented.
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-- Not selected for future implementation.
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-- Not selected for future implementation.
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--
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--
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-- * Reading of internal Program Memory not implemented.
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-- * Reading of internal Program Memory not implemented.
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Line 146... |
signal alu_read_alu_s : boolean;
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signal alu_read_alu_s : boolean;
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signal alu_carry_s : std_logic;
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signal alu_carry_s : std_logic;
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signal alu_aux_carry_s : std_logic;
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signal alu_aux_carry_s : std_logic;
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signal alu_op_s : alu_op_t;
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signal alu_op_s : alu_op_t;
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signal alu_use_carry_s : boolean;
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signal alu_use_carry_s : boolean;
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signal alu_da_low_s : boolean;
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signal alu_da_high_s : boolean;
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signal alu_da_overflow_s : boolean;
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signal alu_p06_temp_reg_s : boolean;
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signal alu_p60_temp_reg_s : boolean;
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-- BUS signals
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-- BUS signals
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signal bus_write_bus_s : boolean;
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signal bus_write_bus_s : boolean;
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signal bus_read_bus_s : boolean;
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signal bus_read_bus_s : boolean;
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signal bus_output_pcl_s : boolean;
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signal bus_output_pcl_s : boolean;
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Line 290... |
carry_i => psw_carry_s,
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carry_i => psw_carry_s,
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carry_o => alu_carry_s,
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carry_o => alu_carry_s,
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aux_carry_i => psw_aux_carry_s,
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aux_carry_i => psw_aux_carry_s,
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aux_carry_o => alu_aux_carry_s,
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aux_carry_o => alu_aux_carry_s,
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alu_op_i => alu_op_s,
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alu_op_i => alu_op_s,
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use_carry_i => alu_use_carry_s
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use_carry_i => alu_use_carry_s,
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da_low_i => alu_da_low_s,
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da_high_i => alu_da_high_s,
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da_overflow_o => alu_da_overflow_s,
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p06_temp_reg_i => alu_p06_temp_reg_s,
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p60_temp_reg_i => alu_p60_temp_reg_s
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);
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);
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bus_mux_b : bus_mux
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bus_mux_b : bus_mux
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port map (
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port map (
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alu_data_i => alu_data_s,
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alu_data_i => alu_data_s,
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Line 419... |
psw_read_psw_o => psw_read_psw_s,
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psw_read_psw_o => psw_read_psw_s,
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psw_read_sp_o => psw_read_sp_s,
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psw_read_sp_o => psw_read_sp_s,
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psw_write_psw_o => psw_write_psw_s,
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psw_write_psw_o => psw_write_psw_s,
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psw_write_sp_o => psw_write_sp_s,
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psw_write_sp_o => psw_write_sp_s,
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alu_carry_i => alu_carry_s,
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alu_carry_i => alu_carry_s,
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alu_aux_carry_i => alu_aux_carry_s,
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alu_op_o => alu_op_s,
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alu_op_o => alu_op_s,
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alu_use_carry_o => alu_use_carry_s,
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alu_use_carry_o => alu_use_carry_s,
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alu_da_low_o => alu_da_low_s,
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alu_da_high_o => alu_da_high_s,
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alu_da_overflow_i => alu_da_overflow_s,
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alu_p06_temp_reg_o => alu_p06_temp_reg_s,
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alu_p60_temp_reg_o => alu_p60_temp_reg_s,
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bus_output_pcl_o => bus_output_pcl_s,
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bus_output_pcl_o => bus_output_pcl_s,
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bus_bidir_bus_o => bus_bidir_bus_s,
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bus_bidir_bus_o => bus_bidir_bus_s,
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clk_multi_cycle_o => clk_multi_cycle_s,
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clk_multi_cycle_o => clk_multi_cycle_s,
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clk_assert_psen_o => clk_assert_psen_s,
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clk_assert_psen_o => clk_assert_psen_s,
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clk_assert_prog_o => clk_assert_prog_s,
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clk_assert_prog_o => clk_assert_prog_s,
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| Line 446... |
Line 457... |
pm_inc_pc_o => pm_inc_pc_s,
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pm_inc_pc_o => pm_inc_pc_s,
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pm_write_pmem_addr_o => pm_write_pmem_addr_s,
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pm_write_pmem_addr_o => pm_write_pmem_addr_s,
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pm_addr_type_o => pm_addr_type_s,
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pm_addr_type_o => pm_addr_type_s,
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psw_special_data_o => psw_special_data_s,
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psw_special_data_o => psw_special_data_s,
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psw_carry_i => psw_carry_s,
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psw_carry_i => psw_carry_s,
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psw_aux_carry_i => psw_aux_carry_s,
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psw_f0_i => psw_f0_s,
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psw_f0_i => psw_f0_s,
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psw_inc_stackp_o => psw_inc_stackp_s,
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psw_inc_stackp_o => psw_inc_stackp_s,
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psw_dec_stackp_o => psw_dec_stackp_s,
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psw_dec_stackp_o => psw_dec_stackp_s,
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psw_write_carry_o => psw_write_carry_s,
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psw_write_carry_o => psw_write_carry_s,
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psw_write_aux_carry_o => psw_write_aux_carry_s,
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psw_write_aux_carry_o => psw_write_aux_carry_s,
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Line 604... |
write_carry_i => psw_write_carry_s,
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write_carry_i => psw_write_carry_s,
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write_aux_carry_i => psw_write_aux_carry_s,
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write_aux_carry_i => psw_write_aux_carry_s,
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write_f0_i => psw_write_f0_s,
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write_f0_i => psw_write_f0_s,
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write_bs_i => psw_write_bs_s,
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write_bs_i => psw_write_bs_s,
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carry_o => psw_carry_s,
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carry_o => psw_carry_s,
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aux_carry_i => alu_aux_carry_s,
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aux_carry_o => psw_aux_carry_s,
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aux_carry_o => psw_aux_carry_s,
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f0_o => psw_f0_s,
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f0_o => psw_f0_s,
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bs_o => psw_bs_s
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bs_o => psw_bs_s
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);
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);
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Line 630... |
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/03/28 13:13:20 arniml
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-- connect control signal for Port 2 expander
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--
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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