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Change log for the T48 uController core
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Change log for the T48 uController core
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=======================================
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=======================================
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Version: $Date: 2005-05-08 15:51:47 $
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Version: $Date: 2005-10-14 23:25:41 $
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Release 0.6 BETA
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----------------
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* Bugfix for "Wrong clock applied to T0"
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* Bugfix for "Wrong clock applied to T0"
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Applied in clock_ctrl.vhd 1.7
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Applied in clock_ctrl.vhd 1.7
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t48_core.vhd 1.8
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t48_core.vhd 1.8
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* Introduced "notri" hierarchy for t8048 and t8039 system.
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* Introduced "notri" hierarchy for t8048 and t8039 system.
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* New Wishbone master module: wb_master.vhd
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* New Wishbone master module: wb_master.vhd
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* New system toplevel: t8050_wb.vhd
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* New system toplevel: t8050_wb.vhd
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Contains the Wishbone master.
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Contains the Wishbone master.
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* Prefixed all design units with 't48_'.
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* Updates for running the core with full xtal clock. Should work now.
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* Move latching of BUS to MSTATE2 in decoder.vhd
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-> sample BUS at the end of RD'
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* Fix a glitch on PCH when an interrupt occurs during external
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program memory fetch in decoder.vhd
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* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted
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by interrupt"
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and "Return address of CALL to Program Memory Bank 1 corrupted
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by interrupt"
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Applied in int.vhd 1.5
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* Bugfix for "MSB of Program Counter changed upon PC increment"
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Applied in pmem_ctrl.vhd 1.4
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Release 0.5 BETA
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Release 0.5 BETA
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----------------
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* Bugfix for "P1 constantly in push-pull mode in t8048"
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* Bugfix for "P1 constantly in push-pull mode in t8048"
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