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Known bugs of the T48 uController core
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Known bugs of the T48 uController core
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======================================
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======================================
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Version: $Date: 2004-06-30 21:25:54 $
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Version: $Date: 2004-09-12 10:17:58 $
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Release 0.3 BETA
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----------------
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*******************************************************************************
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PSENn Timing
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PSENn is erroneously activated during read or write from external memory when
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the read and write strobe signals RDn and WRn are active. This happens when
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code is executed from external Program Memory.
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The problem lies in the decoder module where the PSENn signal is generated
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based on the current machine cycle.
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Fixed in decoder.vhd 1.15
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Added waveform check for PSENn in if_timing.vhd 1.3
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New regression test: white_box/psen_rd_wr_timing
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Fix will be included in next release.
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Release 0.2 BETA
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Release 0.2 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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PSENn Timing
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See above.
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*******************************************************************************
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Program Memory bank can be switched during interrupt
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Program Memory bank can be switched during interrupt
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During an interrupt service routine (i.e. after vectoring to location 3 or 7
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During an interrupt service routine (i.e. after vectoring to location 3 or 7
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of the Program Memory and befor executing the RETR instruction) the Program
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of the Program Memory and befor executing the RETR instruction) the Program
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Memory bank can be switched by executing a JMP or CALL instruction. These
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Memory bank can be switched by executing a JMP or CALL instruction. These
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Release 0.1 BETA
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Release 0.1 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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PSENn Timing
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See above.
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*******************************************************************************
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Program Memory bank can be switched during interrupt
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Program Memory bank can be switched during interrupt
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See above.
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See above.
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******************************************************************************
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******************************************************************************
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