| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Data Memory control unit.
|
-- The Data Memory control unit.
|
-- All accesses to the Data Memory are managed here.
|
-- All accesses to the Data Memory are managed here.
|
--
|
--
|
-- $Id: dmem_ctrl.vhd,v 1.2 2004-04-18 18:58:29 arniml Exp $
|
-- $Id: dmem_ctrl.vhd,v 1.3 2004-04-24 23:44:25 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 75... |
Line 75... |
|
|
end dmem_ctrl;
|
end dmem_ctrl;
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_arith.all;
|
use ieee.numeric_std.all;
|
|
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.to_stdLogic;
|
use work.t48_pack.to_stdLogic;
|
| Line 104... |
Line 104... |
dmem_addr_q)
|
dmem_addr_q)
|
variable stack_addr_v : unsigned(5 downto 0);
|
variable stack_addr_v : unsigned(5 downto 0);
|
begin
|
begin
|
-- default assignment
|
-- default assignment
|
dmem_addr_s <= dmem_addr_q;
|
dmem_addr_s <= dmem_addr_q;
|
|
stack_addr_v := (others => '0');
|
|
|
case addr_type_i is
|
case addr_type_i is
|
when DM_PLAIN =>
|
when DM_PLAIN =>
|
dmem_addr_s <= data_i;
|
dmem_addr_s <= data_i;
|
|
|
| Line 119... |
Line 120... |
-- dmem address 24 - 31: access proper set
|
-- dmem address 24 - 31: access proper set
|
dmem_addr_s(4 downto 3) <= "11";
|
dmem_addr_s(4 downto 3) <= "11";
|
end if;
|
end if;
|
|
|
when DM_STACK =>
|
when DM_STACK =>
|
stack_addr_v := (others => '0');
|
|
-- build address from stack pointer
|
-- build address from stack pointer
|
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
|
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
|
-- dmem address 8 - 23
|
-- dmem address 8 - 23
|
stack_addr_v := stack_addr_v + 8;
|
stack_addr_v := stack_addr_v + 8;
|
|
|
dmem_addr_s <= (others => '0');
|
dmem_addr_s <= (others => '0');
|
dmem_addr_s(5 downto 0) <= conv_std_logic_vector(stack_addr_v, 6);
|
dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
|
|
|
when DM_STACK_HIGH =>
|
when DM_STACK_HIGH =>
|
dmem_addr_s(0) <= '1';
|
dmem_addr_s(0) <= '1';
|
|
|
when others =>
|
when others =>
|
| Line 202... |
Line 202... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2004/04/18 18:58:29 arniml
|
|
-- clean up sensitivity list
|
|
--
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
