Line 1... |
Line 1... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The Data Memory control unit.
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-- The Data Memory control unit.
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-- All accesses to the Data Memory are managed here.
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-- All accesses to the Data Memory are managed here.
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--
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--
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-- $Id: dmem_ctrl.vhd,v 1.2 2004-04-18 18:58:29 arniml Exp $
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-- $Id: dmem_ctrl.vhd,v 1.3 2004-04-24 23:44:25 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 75... |
Line 75... |
|
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end dmem_ctrl;
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end dmem_ctrl;
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|
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|
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library ieee;
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library ieee;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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|
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use work.t48_pack.clk_active_c;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.to_stdLogic;
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use work.t48_pack.to_stdLogic;
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Line 104... |
Line 104... |
dmem_addr_q)
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dmem_addr_q)
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variable stack_addr_v : unsigned(5 downto 0);
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variable stack_addr_v : unsigned(5 downto 0);
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begin
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begin
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-- default assignment
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-- default assignment
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dmem_addr_s <= dmem_addr_q;
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dmem_addr_s <= dmem_addr_q;
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stack_addr_v := (others => '0');
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|
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case addr_type_i is
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case addr_type_i is
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when DM_PLAIN =>
|
when DM_PLAIN =>
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dmem_addr_s <= data_i;
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dmem_addr_s <= data_i;
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|
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Line 119... |
Line 120... |
-- dmem address 24 - 31: access proper set
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-- dmem address 24 - 31: access proper set
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dmem_addr_s(4 downto 3) <= "11";
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dmem_addr_s(4 downto 3) <= "11";
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end if;
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end if;
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|
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when DM_STACK =>
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when DM_STACK =>
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stack_addr_v := (others => '0');
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-- build address from stack pointer
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-- build address from stack pointer
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stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
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stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
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-- dmem address 8 - 23
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-- dmem address 8 - 23
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stack_addr_v := stack_addr_v + 8;
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stack_addr_v := stack_addr_v + 8;
|
|
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dmem_addr_s <= (others => '0');
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dmem_addr_s <= (others => '0');
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dmem_addr_s(5 downto 0) <= conv_std_logic_vector(stack_addr_v, 6);
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dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
|
|
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when DM_STACK_HIGH =>
|
when DM_STACK_HIGH =>
|
dmem_addr_s(0) <= '1';
|
dmem_addr_s(0) <= '1';
|
|
|
when others =>
|
when others =>
|
Line 202... |
Line 202... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2004/04/18 18:58:29 arniml
|
|
-- clean up sensitivity list
|
|
--
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|