OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] [vhdl/] [t48_core-c.vhd] - Diff between revs 4 and 179

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4 Rev 179
Line 1... Line 1...
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- T48 Microcontroller Core
-- T48 Microcontroller Core
--
--
-- $Id: t48_core-c.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
-- $Id: t48_core-c.vhd,v 1.2 2005-06-11 10:08:43 arniml Exp $
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
configuration t48_core_struct_c0 of t48_core is
configuration t48_core_struct_c0 of t48_core is
 
 
  for struct
  for struct
 
 
    for alu_b : alu
    for alu_b : t48_alu
      use configuration work.alu_rtl_c0;
      use configuration work.t48_alu_rtl_c0;
    end for;
    end for;
 
 
    for bus_mux_b : bus_mux
    for bus_mux_b : t48_bus_mux
      use configuration work.bus_mux_rtl_c0;
      use configuration work.t48_bus_mux_rtl_c0;
    end for;
    end for;
 
 
    for clock_ctrl_b : clock_ctrl
    for clock_ctrl_b : t48_clock_ctrl
      use configuration work.clock_ctrl_rtl_c0;
      use configuration work.t48_clock_ctrl_rtl_c0;
    end for;
    end for;
 
 
    for cond_branch_b : cond_branch
    for cond_branch_b : t48_cond_branch
      use configuration work.cond_branch_rtl_c0;
      use configuration work.t48_cond_branch_rtl_c0;
    end for;
    end for;
 
 
    for use_db_bus
    for use_db_bus
      for db_bus_b : db_bus
      for db_bus_b : t48_db_bus
        use configuration work.db_bus_rtl_c0;
        use configuration work.t48_db_bus_rtl_c0;
      end for;
      end for;
    end for;
    end for;
 
 
    for decoder_b : decoder
    for decoder_b : t48_decoder
      use configuration work.decoder_rtl_c0;
      use configuration work.t48_decoder_rtl_c0;
    end for;
    end for;
 
 
    for dmem_ctrl_b : dmem_ctrl
    for dmem_ctrl_b : t48_dmem_ctrl
      use configuration work.dmem_ctrl_rtl_c0;
      use configuration work.t48_dmem_ctrl_rtl_c0;
    end for;
    end for;
 
 
    for use_timer
    for use_timer
      for timer_b : timer
      for timer_b : t48_timer
        use configuration work.timer_rtl_c0;
        use configuration work.t48_timer_rtl_c0;
      end for;
      end for;
    end for;
    end for;
 
 
    for use_p1
    for use_p1
      for p1_b : p1
      for p1_b : t48_p1
        use configuration work.p1_rtl_c0;
        use configuration work.t48_p1_rtl_c0;
      end for;
      end for;
    end for;
    end for;
 
 
    for use_p2
    for use_p2
      for p2_b : p2
      for p2_b : t48_p2
        use configuration work.p2_rtl_c0;
        use configuration work.t48_p2_rtl_c0;
      end for;
      end for;
    end for;
    end for;
 
 
    for pmem_ctrl_b : pmem_ctrl
    for pmem_ctrl_b : t48_pmem_ctrl
      use configuration work.pmem_ctrl_rtl_c0;
      use configuration work.t48_pmem_ctrl_rtl_c0;
    end for;
    end for;
 
 
    for psw_b : psw
    for psw_b : t48_psw
      use configuration work.psw_rtl_c0;
      use configuration work.t48_psw_rtl_c0;
    end for;
    end for;
 
 
  end for;
  end for;
 
 
end t48_core_struct_c0;
end t48_core_struct_c0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.